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Searched refs:BIT15 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/staging/rtl8723bs/include/
A Drtl8723b_spec.h201 #define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is …
229 #define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrupt 2 */
A Dosdep_service.h32 #define BIT15 0x00008000 macro
A Dhal_com_reg.h262 #define CAM_VALID BIT15
/linux/drivers/net/wireless/realtek/rtlwifi/btcoexist/
A Dhalbt_precomp.h46 #define BIT15 0x00008000 macro
/linux/include/uapi/linux/
A Dsynclink.h34 #define BIT15 0x8000 macro
/linux/drivers/scsi/
A Ddc395x.h61 #define BIT15 0x00008000 macro
/linux/drivers/tty/
A Dsynclink_gt.c191 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
2046 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8)); in isr_rxdata()
4121 val = BIT15 + BIT14 + BIT0; in async_mode()
4173 val |= BIT15 + BIT13; in sync_mode()
4176 case MGSL_MODE_BISYNC: val |= BIT15; break; in sync_mode()
4248 val |= BIT15 + BIT13; in sync_mode()
4251 case MGSL_MODE_BISYNC: val |= BIT15; break; in sync_mode()
4357 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); in sync_mode()
/linux/drivers/staging/rtl8723bs/hal/
A Dhal_com.c980 PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target); in rtw_bb_rf_gain_offset()
/linux/drivers/scsi/lpfc/
A Dlpfc_hw4.h782 #define LPFC_SLI4_INTR15 BIT15

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