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Searched refs:CAN1 (Results 1 – 25 of 29) sorted by relevance

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/linux/Documentation/devicetree/bindings/net/can/
A Dst,stm32-bxcan.yaml69 SRAM memory shared by the two bxCAN cells (CAN1 primary and CAN2
92 resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
93 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
A Drenesas,rcar-canfd.yaml126 - description: CAN1 error interrupt
127 - description: CAN1 transmit interrupt
128 - description: CAN1 transmit/receive FIFO receive completion interrupt
/linux/arch/arm64/boot/dts/renesas/
A Dr9a07g044c2-smarc.dts14 * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
15 * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
A Dr9a07g043u11-smarc.dts14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
/linux/arch/arm64/boot/dts/freescale/
A Dimx8-apalis-eval-v1.1.dtsi8 /* Apalis CAN1 */
A Dimx8-apalis-eval-v1.2.dtsi56 /* Apalis CAN1 */
A Dimx8-apalis-ixora-v1.1.dtsi78 /* Apalis CAN1 */
A Dimx8-apalis-ixora-v1.2.dtsi110 /* Apalis CAN1 */
A Dimx8mp-evk.dts605 "CAN1/I2C5_SEL",
629 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
630 * LOW: CAN1 (default, pull-down)
A Dimx8-apalis-v1.1.dtsi268 /* Apalis CAN1 */
955 /* Apalis CAN1 */
A Dimx8-ss-dma.dtsi421 * CAN1 shares CAN0's clock and to enable CAN0's clock it
/linux/arch/riscv/boot/dts/renesas/
A Dr9a07g043f01-smarc.dts14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
/linux/include/dt-bindings/clock/
A Dxlnx-zynqmp-clk.h78 #define CAN1 66 macro
/linux/drivers/net/can/sja1000/
A DKconfig107 tristate "TS-CAN1 PC104 boards"
111 https://www.embeddedts.com/products/TS-CAN1
/linux/arch/powerpc/boot/dts/
A Dpcm030.dts31 /* PSC2 port is used by CAN1/2 */
A Dpcm032.dts33 /* PSC2 port is used by CAN1/2 */
/linux/arch/arm/boot/dts/renesas/
A Dr9a06g032-rzn1d400-db.dts33 /* Assuming CN10/CN11 are wired for CAN1 */
/linux/arch/arm/boot/dts/st/
A Dstm32f746.dtsi365 resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
366 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
375 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
A Dstm32f429.dtsi370 resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
371 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
380 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
/linux/drivers/pinctrl/
A Dpinctrl-lpc18xx.c259 LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD);
260 LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND);
294 LPC_P(4,8, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
295 LPC_P(4,9, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
386 LPC_P(e,0, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
387 LPC_P(e,1, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
/linux/arch/arm/boot/dts/nvidia/
A Dtegra30-apalis-v1.1.dtsi106 /* Apalis CAN1 on SPI6 */
1073 /* SPI6: CAN1 */
A Dtegra30-apalis.dtsi105 /* Apalis CAN1 on SPI6 */
1056 /* SPI6: CAN1 */
/linux/arch/arm/boot/dts/microchip/
A Dat91-sam9x60ek.dts450 AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN /* Enable CAN1 mux */
/linux/arch/arm/boot/dts/nxp/imx/
A Dimx6ull-colibri.dtsi478 pinctrl_gpio7: gpio7grp { /* CAN1 */
A Dimx6qdl-kontron-samx6i.dtsi240 /* CAN1 */

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