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Searched refs:CCR (Results 1 – 25 of 26) sorted by relevance

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/linux/arch/arm/mach-omap1/
A Domap-dma.c145 ccr = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
149 p->dma_write(ccr, CCR, lch); in omap_set_dma_transfer_params()
187 l = p->dma_read(CCR, lch); in omap_set_dma_src_params()
190 p->dma_write(l, CCR, lch); in omap_set_dma_src_params()
255 l = p->dma_read(CCR, lch); in omap_set_dma_dest_params()
258 p->dma_write(l, CCR, lch); in omap_set_dma_dest_params()
430 p->dma_write(0, CCR, lch); in omap_free_dma()
497 l = p->dma_read(CCR, lch); in omap_start_dma()
510 p->dma_write(l, CCR, lch); in omap_start_dma()
523 l = p->dma_read(CCR, lch); in omap_stop_dma()
[all …]
A Ddma.c57 [CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
214 l = dma_read(CCR, lch); in omap1_clear_dma()
216 dma_write(l, CCR, lch); in omap1_clear_dma()
/linux/drivers/dma/
A Dtxx9dmac.h77 TXX9_DMA_REG32(CCR); /* Channel Control Register */
87 u32 CCR; member
278 desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
280 desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
294 desc->hwdesc.CCR = ccr; in txx9dmac_desc_set_nosimple()
298 desc->hwdesc32.CCR = ccr; in txx9dmac_desc_set_nosimple()
A Dtxx9dmac.c295 channel64_readl(dc, CCR), in txx9dmac_dump_regs()
307 channel32_readl(dc, CCR), in txx9dmac_dump_regs()
313 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST); in txx9dmac_reset_chan()
326 channel_writel(dc, CCR, 0); in txx9dmac_reset_chan()
365 channel64_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
386 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
391 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
480 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
493 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
A Dpl330.c340 CCR, enumerator
1270 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); in _dregs()
1276 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); in _dregs()
1425 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); in _setup_req()
/linux/arch/arm/mach-imx/
A Dpm-imx6.c31 #define CCR 0x0 macro
255 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
258 writel_relaxed(val, ccm_base + CCR); in imx6_enable_rbc()
261 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
264 writel(val, ccm_base + CCR); in imx6_enable_rbc()
288 val = readl_relaxed(ccm_base + CCR); in imx6q_enable_wb()
291 writel_relaxed(val, ccm_base + CCR); in imx6q_enable_wb()
/linux/drivers/clocksource/
A Dtimer-atmel-tcb.c104 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR)); in tc_clksrc_resume()
166 writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); in tc_shutdown()
215 ATMEL_TC_REG(2, CCR)); in tc_set_periodic()
225 tcaddr + ATMEL_TC_REG(2, CCR)); in tc_next_event()
325 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_dual_chan()
333 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); in tcb_setup_dual_chan()
349 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_single_chan()
/linux/drivers/pwm/
A Dpwm-atmel-tcb.c165 ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_disable()
170 ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_disable()
252 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_enable()
515 ATMEL_TC_REG(channel, CCR)); in atmel_tcb_pwm_resume()
/linux/arch/arm/mach-omap2/
A Ddma.c54 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
/linux/Documentation/translations/zh_CN/arch/parisc/
A Dregisters.rst28 CR10 (CCR) FPU延迟保存*
/linux/Documentation/translations/zh_TW/arch/parisc/
A Dregisters.rst28 CR10 (CCR) FPU延遲保存*
/linux/drivers/counter/
A Dmicrochip-tcb-capture.c130 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR), in mchp_tc_count_function_write()
137 ATMEL_TC_REG(priv->channel[1], CCR), in mchp_tc_count_function_write()
/linux/include/sound/
A Demu10k1.h475 #define CCR 0x09 /* Cache control register */ macro
476 SUB_REG(CCR, CACHEINVALIDSIZE, 0xfe000000) /* Number of invalid samples before the read address */
482 SUB_REG(CCR, READADDRESS, 0x003f0000) /* Next cached sample to play */
483 SUB_REG(CCR, LOOPINVALSIZE, 0x0000fe00) /* Number of invalid samples in cache prior to loop */
486 SUB_REG(CCR, CACHELOOPADDRHI, 0x000000ff) /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
/linux/drivers/dma/ti/
A Domap-dma.c457 omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); in omap_dma_start()
469 val = omap_dma_chan_read(c, CCR); in omap_dma_drain_chan()
495 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
504 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
506 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
517 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
587 omap_dma_chan_write(c, CCR, d->ccr); in omap_dma_start_desc()
931 uint32_t ccr = omap_dma_chan_read(c, CCR); in omap_dma_tx_status()
1542 if (omap_dma_chan_read(c, CCR) & CCR_ENABLE) in omap_dma_busy()
/linux/sound/soc/intel/keembay/
A Dkmb_platform.h23 #define CCR 0x010 macro
A Dkmb_platform.c657 writel(kmb_i2s->ccr, kmb_i2s->i2s_base + CCR); in kmb_dai_hw_params()
/linux/sound/soc/dwc/
A Dlocal.h24 #define CCR 0x010 macro
A Ddwc-i2s.c324 i2s_write_reg(dev->i2s_base, CCR, dev->ccr); in dw_i2s_hw_params()
/linux/include/linux/
A Domap-dma.h153 CSDP, CCR, CICR, CSR, enumerator
/linux/Documentation/arch/parisc/
A Dregisters.rst18 CR10 (CCR) lazy FPU saving*
/linux/sound/pci/emu10k1/
A Demu10k1_callback.c436 CCR, REG_VAL_PUT(CCR_CACHEINVALIDSIZE, 64), in start_voice()
A Demu10k1_main.c58 CCR, 0, in snd_emu10k1_voice_init()
1701 CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP,
A Demupcm.c576 snd_emu10k1_ptr_write(emu, CCR, voice + 1, ccr); in snd_emu10k1_playback_fill_cache()
578 snd_emu10k1_ptr_write(emu, CCR, voice, ccr); in snd_emu10k1_playback_fill_cache()
/linux/Documentation/arch/powerpc/
A Dtransactional_memory.rst63 Checkpointed registers include all GPRs, FPRs, VRs/VSRs, LR, CCR/CR, CTR, FPCSR
/linux/drivers/tty/
A Dsynclink_gt.c369 #define CCR 0x89 /* clock control */ macro
3815 wr_reg8(info, CCR, 0x49); in enable_loopback()
4098 wr_reg8(info, CCR, 0x69); in async_mode()
4311 wr_reg8(info, CCR, (unsigned char)val); in sync_mode()

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