| /linux/arch/arm/mach-omap1/ |
| A D | clock_data.c | 607 CLK(NULL, "ck_sossi", &sossi_ck.hw, CK_16XX),
628 CLK(NULL, "tc1_ck", &tc1_ck.hw, CK_16XX),
629 CLK(NULL, "tc2_ck", &tc2_ck.hw, CK_16XX),
634 CLK(NULL, "rhea1_ck", &rhea1_ck.hw, CK_16XX),
635 CLK(NULL, "rhea2_ck", &rhea2_ck.hw, CK_16XX),
641 CLK(NULL, "uart1_ck", &uart1_7xx.hw, CK_7XX),
643 CLK(NULL, "uart2_ck", &uart2_7xx.hw, CK_7XX),
651 CLK(NULL, "mclk", &mclk_16xx.hw, CK_16XX),
653 CLK(NULL, "bclk", &bclk_16xx.hw, CK_16XX),
655 CLK("mmci-omap.0", "fck", &mmc3_ck.hw, CK_7XX),
[all …]
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| A D | clock.h | 25 #define CLK(dev, con, ck, cp) \ macro
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| /linux/drivers/gpu/drm/sprd/ |
| A D | megacores_pll.c | 17 #define CLK 0 macro
131 regmap_write(regmap, 0x31, val[CLK]); in dphy_set_timing_reg()
137 regmap_write(regmap, 0x90, val[CLK]); in dphy_set_timing_reg()
144 regmap_write(regmap, 0x32, val[CLK]); in dphy_set_timing_reg()
150 regmap_write(regmap, 0x91, val[CLK]); in dphy_set_timing_reg()
157 regmap_write(regmap, 0x33, val[CLK]); in dphy_set_timing_reg()
163 regmap_write(regmap, 0x92, val[CLK]); in dphy_set_timing_reg()
170 regmap_write(regmap, 0x34, val[CLK]); in dphy_set_timing_reg()
239 val[DATA] = val[CLK]; in dphy_timing_config()
276 val[DATA] = val[CLK]; in dphy_timing_config()
[all …]
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| /linux/arch/arm/boot/dts/st/ |
| A D | ste-dbx5x0-pinctrl.dtsi | 267 pins = "GPIO23_AA4"; /* CLK */
300 pins = "GPIO23_AA4"; /* CLK */
315 pins = "GPIO23_AA4"; /* CLK */
341 pins = "GPIO23_AA4"; /* CLK */
355 pins = "GPIO208_AH16"; /* CLK */
375 pins = "GPIO208_AH16"; /* CLK */
396 pins = "GPIO208_AH16"; /* CLK */
412 pins = "GPIO208_AH16"; /* CLK */
435 pins = "GPIO128_A5"; /* CLK */
459 pins = "GPIO128_A5"; /* CLK */
[all …]
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| A D | ste-href-family-pinctrl.dtsi | 29 "GPIO217_AH12"; /* CLK */
49 pins = "GPIO217_AH12"; /* CLK */
66 pins = "GPIO217_AH12"; /* CLK */
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| A D | stm32f7-pinctrl.dtsi | 241 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
254 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
272 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1 CLK */
283 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
296 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
314 <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC2 CLK */
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| /linux/Documentation/devicetree/bindings/display/ti/ |
| A D | ti,omap5-dss.txt | 77 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
99 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
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| A D | ti,omap4-dss.txt | 96 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
118 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
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| A D | ti,dra7-dss.txt | 73 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
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| A D | ti,omap3-dss.txt | 86 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/ |
| A D | ddc_regs.h | 158 DDC_REG_LIST(CLK, id)\
168 DDC_VGA_REG_LIST(CLK)\
187 DDC_REG_LIST_DCN2(CLK, id)\
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| /linux/Documentation/devicetree/bindings/media/ |
| A D | renesas,drif.yaml | 18 | |-----SCK------->|CLK |
26 CLK & SYNC. Each internal channel has its own dedicated resources like
31 The internal channels sharing the CLK & SYNC are tied together by their
162 # | |-----SCK------->|CLK |
219 # | |-----SCK------->|CLK |
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| /linux/arch/arm64/boot/dts/amlogic/ |
| A D | meson-gxl-s905x-khadas-vim.dts | 189 "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
198 "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
201 "Bluetooth PCM SYNC", "Bluetooth PCM CLK",
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| A D | meson-gxbb-nanopi-k2.dts | 266 "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
285 "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
288 "Bluetooth PCM SYNC", "Bluetooth PCM CLK",
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| /linux/arch/arm64/boot/dts/renesas/ |
| A D | r9a07g043u11-smarc-du-adv7513.dtso | 59 pinmux = <RZG2L_PORT_PINMUX(11, 3, 6)>; /* CLK */
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| /linux/Documentation/devicetree/bindings/iio/adc/ |
| A D | ti,ads1298.yaml | 40 description: Optional 2.048 MHz external source clock on CLK pin
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| /linux/arch/arm/boot/dts/allwinner/ |
| A D | sun8i-h2-plus-bananapi-m2-zero.dts | 234 "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
241 "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1",
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| A D | sun7i-a20-bananapi.dts | 229 "SD0-D1", "SD0-D0", "SD0-CLK", "SD0-CMD", "SD0-D3",
246 "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI",
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| /linux/Documentation/devicetree/bindings/hwmon/ |
| A D | gmt,g762.yaml | 37 description: a fixed clock providing input clock frequency on CLK
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | renesas,rzv2h-cpg.yaml | 44 used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
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| /linux/Documentation/devicetree/bindings/sound/ |
| A D | microchip,sama7g5-pdmc.yaml | 52 or falling) of the CLK line. A microphone is represented as a pair of DS
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| A D | hw_factory_dcn20.c | 128 DDC_GPIO_VGA_REG_LIST(CLK),
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| A D | hw_factory_dcn30.c | 135 DDC_GPIO_VGA_REG_LIST(CLK),
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
| A D | hw_factory_dcn315.c | 129 DDC_GPIO_VGA_REG_LIST(CLK),
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/ |
| A D | hw_factory_dcn32.c | 139 DDC_GPIO_VGA_REG_LIST(CLK),
|