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Searched refs:CLKID_FCLK_DIV5 (Results 1 – 21 of 21) sorted by relevance

/linux/include/dt-bindings/clock/
A Damlogic,a1-pll-clkc.h21 #define CLKID_FCLK_DIV5 8 macro
A Damlogic,c3-pll-clkc.h21 #define CLKID_FCLK_DIV5 11 macro
A Damlogic,s4-pll-clkc.h19 #define CLKID_FCLK_DIV5 9 macro
A Daxg-clkc.h16 #define CLKID_FCLK_DIV5 5 macro
A Dgxbb-clkc.h15 #define CLKID_FCLK_DIV5 7 macro
A Dmeson8b-clkc.h15 #define CLKID_FCLK_DIV5 8 macro
A Dg12a-clkc.h16 #define CLKID_FCLK_DIV5 5 macro
/linux/Documentation/devicetree/bindings/clock/
A Damlogic,a1-peripherals-clkc.yaml69 <&clkc_pll CLKID_FCLK_DIV5>,
/linux/drivers/clk/meson/
A Da1-pll.c283 [CLKID_FCLK_DIV5] = &fclk_div5.hw,
A Dc3-pll.c635 [CLKID_FCLK_DIV5] = &fclk_div5.hw,
A Ds4-pll.c746 [CLKID_FCLK_DIV5] = &s4_fclk_div5.hw,
A Dmeson8b.c2786 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2990 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
3205 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
A Dgxbb.c2740 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
2948 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
A Dg12a.c4386 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4613 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4881 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
A Daxg.c1901 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
/linux/arch/arm64/boot/dts/amlogic/
A Dmeson-a1.dtsi303 <&clkc_pll CLKID_FCLK_DIV5>,
A Damlogic-c3.dtsi129 <&clkc_pll CLKID_FCLK_DIV5>,
A Dmeson-sm1.dtsi165 <&clkc CLKID_FCLK_DIV5>;
A Dmeson-s4.dtsi112 <&clkc_pll CLKID_FCLK_DIV5>,
/linux/arch/arm/boot/dts/amlogic/
A Dmeson8b.dtsi705 <&clkc CLKID_FCLK_DIV5>,
A Dmeson8.dtsi730 <&clkc CLKID_FCLK_DIV5>,

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