Searched refs:CLK_DIV_8 (Results 1 – 7 of 7) sorted by relevance
606 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) { in rts5228_pci_switch_clock()636 } else if (div == CLK_DIV_8) { in rts5228_pci_switch_clock()
685 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) { in rts5261_pci_switch_clock()715 } else if (div == CLK_DIV_8) { in rts5261_pci_switch_clock()
755 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) { in rts5264_pci_switch_clock()785 } else if (div == CLK_DIV_8) { in rts5264_pci_switch_clock()
767 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) { in rtsx_pci_switch_clock()
307 #define CLK_DIV_8 0x03 macro
458 #define CLK_DIV_8 0x04 macro
54 #define CLK_DIV_8 0x04 macro
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