Searched refs:CLK_PLL (Results 1 – 4 of 4) sorted by relevance
| /linux/drivers/clk/ |
| A D | clk-loongson2.c | 70 #define CLK_PLL(_id, _name, _offset, _mshift, _mwidth, \ macro
116 CLK_PLL(LOONGSON2_NODE_PLL, "pll_node", 0, 16, 8, 8, 6),
117 CLK_PLL(LOONGSON2_DDR_PLL, "pll_ddr", 0x8, 16, 8, 8, 6),
118 CLK_PLL(LOONGSON2_DC_PLL, "pll_soc", 0x10, 16, 8, 8, 6),
119 CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x18, 16, 8, 8, 6),
120 CLK_PLL(LOONGSON2_PIX1_PLL, "pll_pix1", 0x20, 16, 8, 8, 6),
164 CLK_PLL(LOONGSON2_DC_PLL, "pll_0", 0, 21, 9, 32, 6),
165 CLK_PLL(LOONGSON2_DDR_PLL, "pll_1", 0x10, 21, 9, 32, 6),
166 CLK_PLL(LOONGSON2_NODE_PLL, "pll_2", 0x20, 21, 9, 32, 6),
167 CLK_PLL(LOONGSON2_PIX0_PLL, "pll_pix0", 0x30, 21, 9, 32, 6),
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| A D | clk-bm1880.c | 174 #define CLK_PLL(_id, _name, _parent, _reg, _flags) { \ macro
206 CLK_PLL(BM1880_CLK_MPLL, "clk_mpll", bm1880_pll_parent,
208 CLK_PLL(BM1880_CLK_SPLL, "clk_spll", bm1880_pll_parent,
210 CLK_PLL(BM1880_CLK_FPLL, "clk_fpll", bm1880_pll_parent,
212 CLK_PLL(BM1880_CLK_DDRPLL, "clk_ddrpll", bm1880_pll_parent,
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| /linux/drivers/clk/renesas/ |
| A D | r7s9210-cpg-mssr.c | 51 CLK_PLL, enumerator
63 DEF_BASE(".pll", CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN),
66 DEF_FIXED("p1c", R7S9210_CLK_P1C, CLK_PLL, 16, 1),
77 DEF_FIXED("i", R7S9210_CLK_I, CLK_PLL, 2, 1),
78 DEF_FIXED("g", R7S9210_CLK_G, CLK_PLL, 4, 1),
79 DEF_FIXED("b", R7S9210_CLK_B, CLK_PLL, 8, 1),
80 DEF_FIXED("p1", R7S9210_CLK_P1, CLK_PLL, 16, 1),
81 DEF_FIXED("p0", R7S9210_CLK_P0, CLK_PLL, 32, 1),
177 case CLK_PLL: in rza2_cpg_clk_register()
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| /linux/drivers/clk/microchip/ |
| A D | clk-mpfs.c | 136 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ macro
146 CLK_PLL(CLK_MSSPLL_INTERNAL, "clk_msspll_internal", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT,
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