Home
last modified time | relevance | path

Searched refs:CLK_TOP_APLL12_CK_DIV2 (Results 1 – 12 of 12) sorted by relevance

/linux/include/dt-bindings/clock/
A Dmt8516-clk.h198 #define CLK_TOP_APLL12_CK_DIV2 166 macro
A Dmediatek,mt8365-clk.h124 #define CLK_TOP_APLL12_CK_DIV2 114 macro
A Dmt8186-clk.h152 #define CLK_TOP_APLL12_CK_DIV2 133 macro
A Dmediatek,mt8188-clk.h192 #define CLK_TOP_APLL12_CK_DIV2 181 macro
/linux/Documentation/devicetree/bindings/sound/
A Dmt8186-afe-pcm.yaml143 <&topckgen 133>, //CLK_TOP_APLL12_CK_DIV2
A Dmediatek,mt8188-afe.yaml198 <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2
/linux/drivers/clk/mediatek/
A Dclk-mt8186-topckgen.c676 DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "apll_i2s2_mck_sel",
A Dclk-mt8516.c483 DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
A Dclk-mt8167.c672 DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
A Dclk-mt8188-topckgen.c1184 DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "top_i2so1", 0x0320, 2, 0x0328, 8, 16),
A Dclk-mt8365.c557 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "apll_i2s2_sel",
/linux/arch/arm64/boot/dts/mediatek/
A Dmt8186.dtsi1518 <&topckgen CLK_TOP_APLL12_CK_DIV2>,

Completed in 29 milliseconds