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Searched refs:CLK_TOP_APLL5 (Results 1 – 4 of 4) sorted by relevance

/linux/include/dt-bindings/clock/
A Dmediatek,mt8188-clk.h87 #define CLK_TOP_APLL5 76 macro
A Dmt8195-clk.h108 #define CLK_TOP_APLL5 96 macro
/linux/drivers/clk/mediatek/
A Dclk-mt8188-topckgen.c1140 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
A Dclk-mt8195-topckgen.c1112 MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",

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