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Searched refs:CLK_TOP_CAMTG1_SEL (Results 1 – 4 of 4) sorted by relevance

/linux/include/dt-bindings/clock/
A Dmt6765-clk.h138 #define CLK_TOP_CAMTG1_SEL 103 macro
A Dmediatek,mt8365-clk.h78 #define CLK_TOP_CAMTG1_SEL 68 macro
/linux/drivers/clk/mediatek/
A Dclk-mt8365.c426 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
A Dclk-mt6765.c392 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,

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