Searched refs:CLK_TOP_VENC_SEL (Results 1 – 17 of 17) sorted by relevance
| /linux/Documentation/devicetree/bindings/media/ |
| A D | mediatek,vcodec-encoder.yaml | 162 clocks = <&topckgen CLK_TOP_VENC_SEL>;
164 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
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| /linux/include/dt-bindings/clock/ |
| A D | mt8135-clk.h | 86 #define CLK_TOP_VENC_SEL 75 macro
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| A D | mediatek,mt6795-clk.h | 96 #define CLK_TOP_VENC_SEL 85 macro
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| A D | mt8173-clk.h | 98 #define CLK_TOP_VENC_SEL 88 macro
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| A D | mt2712-clk.h | 135 #define CLK_TOP_VENC_SEL 104 macro
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| A D | mt8192-clk.h | 63 #define CLK_TOP_VENC_SEL 51 macro
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| /linux/Documentation/devicetree/bindings/soc/mediatek/ |
| A D | scpsys.txt | 68 <&topckgen CLK_TOP_VENC_SEL>,
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| /linux/drivers/clk/mediatek/ |
| A D | clk-mt6795-topckgen.c | 462 TOP_MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x50, 16, 4, 23, 0),
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| A D | clk-mt8173-topckgen.c | 541 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),
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| A D | clk-mt8135.c | 373 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
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| A D | clk-mt2712.c | 652 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x050, 16, 4, 23),
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| A D | clk-mt8192.c | 667 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",
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| /linux/Documentation/devicetree/bindings/power/ |
| A D | mediatek,power-controller.yaml | 165 <&topckgen CLK_TOP_VENC_SEL>;
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| /linux/arch/arm64/boot/dts/mediatek/ |
| A D | mt8173.dtsi | 466 <&topckgen CLK_TOP_VENC_SEL>;
1467 clocks = <&topckgen CLK_TOP_VENC_SEL>;
1469 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
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| A D | mt2712e.dtsi | 287 <&topckgen CLK_TOP_VENC_SEL>,
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| A D | mt6795.dtsi | 311 <&topckgen CLK_TOP_VENC_SEL>;
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| A D | mt8192.dtsi | 628 clocks = <&topckgen CLK_TOP_VENC_SEL>,
1827 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
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