Searched refs:Counter (Results 1 – 25 of 76) sorted by relevance
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19 typedef u_long Counter ; typedef29 Counter count ;195 Counter fddiMACFrame_Ct ;196 Counter fddiMACCopied_Ct ;197 Counter fddiMACTransmit_Ct ;198 Counter fddiMACToken_Ct ;199 Counter fddiMACError_Ct ;200 Counter fddiMACLost_Ct ;203 Counter fddiMACRingOp_Ct ;212 Counter fddiMACOld_Lost_Ct ;[all …]
4 Generic Counter Interface353 registered to the Counter core component for use by the Counter385 | Counter sysfs | | Counter chrdev |388 | standard Counter | | standard Counter |425 | Counter sysfs | | Counter chrdev |428 | standard Counter | | standard Counter |460 Counter core465 Counter sysfs474 Counter chrdev501 Counter events[all …]
164 - CTR (Counter) mode (NIST SP800-38A)181 - CTR (Counter) mode (NIST SP800-38A)212 - CTR (Counter) mode (NIST SP800-38A)243 - CTR (Counter) mode (NIST SP800-38A)261 - CTR (Counter) mode (NIST SP800-38A)276 CCM (Counter with Cipher Block Chaining-Message Authentication Code)292 CCM (Counter with Cipher Block Chaining-Message Authentication Code)308 GCM (Galois/Counter Mode) authenticated encryption mode (NIST SP800-38D)
3 # Counter devices22 tristate "Counter support"24 This enables counter device support through the Generic Counter82 tristate "Microchip Timer Counter Capture driver"87 Select this option to enable the Microchip Timer Counter Block
7 title: Arm SMMUv3 Performance Monitor Counter Group14 An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
12 The Counter Enable signal CNT_EN is used54 | Prescaler +-> | Counter | +-> | Master | TRGO(2)119 Counter is always ON.
50 whether Replay Protected Monotonic Counter support has been enabled.61 whether an Replay Protected Monotonic Counter supported SPI is installed
5 Indicates the cascading of Counts on Counter X.14 Counter X.342 Size of the Counter events queue in number of struct351 the Counter. This should match the name of the device as it359 belonging to the Counter.366 belonging to the Counter.
1 OMAP Counter-32K bindings
11 is one register for each counter. Counter 0 is special in that it always counts81 --Counter N MASK COMP register - including AXI_ID and AXI_MASKING.82 --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT.
94 selected by configuring BDF to "bdf". Counter only counts the bandwidth of120 Counter counts when TLP length within the specified range. You can set the
1 * Cirrus Logic CLPS711X Timer Counter
7 title: Cadence TTC - Triple Timer Counter
7 title: Realtek Otto SoCs Timer/Counter
7 title: NXP System Counter Module(sys_ctr)
123 Ring / Netdev Counter137 .. flat-table:: Ring / Software Port Counter Table140 * - Counter745 .. flat-table:: vPort Counter Table748 * - Counter896 .. flat-table:: Physical Port Counter Table899 * - Counter1208 .. flat-table:: Priority Port Counter Table1211 * - Counter1285 .. flat-table:: Device Counter Table[all …]
4 Ingenic JZ47xx SoCs Timer/Counter Unit hardware7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
51 /* 64-bit Global Free Running Counter */
7 title: Atmel Timer Counter Block13 The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each
26 load_mem_type_cnt = collections.Counter()
30 - Counter value for the rpmb device will be read to stdout.
14 CR 0 (Recovery Counter) used for ptrace81 R (Recovery Counter trap) 0
29 [Fixed Counter: Counts the number of instructions retired. Unit: cpu_atom]31 [Number of instructions retired. Fixed Counter - architectural event. Unit: cpu_core]
29 14 counter Counter
93 Support the clocks of the Timer/Counter Unit (TCU) of the Ingenic
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