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Searched refs:DCN_BASE__INST0_SEG3 (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_dcn315.c36 #define DCN_BASE__INST0_SEG3 0x00009000 macro
A Ddmub_dcn316.c36 #define DCN_BASE__INST0_SEG3 0x00009000 macro
A Ddmub_dcn314.c36 #define DCN_BASE__INST0_SEG3 0x00009000 macro
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
A Dhw_factory_dcn315.c48 #define DCN_BASE__INST0_SEG3 0x00009000 macro
A Dhw_translate_dcn315.c41 #define DCN_BASE__INST0_SEG3 0x00009000 macro
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/
A Dirq_service_dcn315.c41 #define DCN_BASE__INST0_SEG3 0x00009000 macro
/linux/drivers/gpu/drm/amd/include/
A Dnavi10_ip_offset.h270 #define DCN_BASE__INST0_SEG3 0x00009000 macro
A Ddimgrey_cavefish_ip_offset.h364 #define DCN_BASE__INST0_SEG3 0x00009000 macro
A Dsienna_cichlid_ip_offset.h371 #define DCN_BASE__INST0_SEG3 0x00009000 macro
A Dbeige_goby_ip_offset.h442 #define DCN_BASE__INST0_SEG3 0x00009000 macro
A Drenoir_ip_offset.h1370 #define DCN_BASE__INST0_SEG3 0 macro
A Dvega10_ip_offset.h306 #define DCN_BASE__INST0_SEG3 0 macro
A Dvangogh_ip_offset.h453 #define DCN_BASE__INST0_SEG3 0x00009000 macro
A Dyellow_carp_offset.h388 #define DCN_BASE__INST0_SEG3 0x00009000 macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
A Ddcn316_resource.c97 #define DCN_BASE__INST0_SEG3 0x00009000 macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
A Ddcn314_resource.c107 #define DCN_BASE__INST0_SEG3 0x00009000 macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
A Ddcn315_resource.c99 #define DCN_BASE__INST0_SEG3 0x00009000 macro

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