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Searched refs:DISPLAY_VER (Results 1 – 25 of 84) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
A Dintel_display_device.h120 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
131 #define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
137 #define HAS_FW_BLC(i915) (DISPLAY_VER(i915) >= 3)
138 #define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
144 #define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12)
147 #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
151 #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12)
155 #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
156 #define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13)
157 #define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20)
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A Di9xx_plane.c213 if (DISPLAY_VER(dev_priv) >= 4 && in i9xx_plane_ctl()
252 if (DISPLAY_VER(dev_priv) >= 4) in i9xx_check_plane_surface()
366 if (DISPLAY_VER(dev_priv) < 5) in i9xx_plane_ctl_crtc()
429 if (DISPLAY_VER(dev_priv) < 4) { in i9xx_plane_update_noarm()
466 if (DISPLAY_VER(dev_priv) >= 4) in i9xx_plane_update_arm()
502 if (DISPLAY_VER(dev_priv) >= 4) in i9xx_plane_update_arm()
545 if (DISPLAY_VER(dev_priv) >= 4) in i9xx_plane_disable_arm()
693 if (DISPLAY_VER(dev_priv) >= 5) in i9xx_plane_get_hw_state()
904 if (DISPLAY_VER(dev_priv) >= 4) in intel_primary_plane_create()
1004 if (DISPLAY_VER(dev_priv) >= 4) in intel_primary_plane_create()
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A Dintel_fbc.c171 if (DISPLAY_VER(display) >= 11) in skl_fbc_min_cfb_stride()
194 if (DISPLAY_VER(display) >= 9) in _intel_fbc_cfb_stride()
219 if (DISPLAY_VER(display) >= 8) in intel_fbc_max_cfb_height()
280 if (DISPLAY_VER(display) == 2) in i8xx_fbc_ctl()
343 if (DISPLAY_VER(display) == 4) { in i8xx_fbc_activate()
453 if (DISPLAY_VER(display) < 6) in g4x_dpfc_ctl()
642 if (DISPLAY_VER(display) >= 20) in ivb_dpfc_ctl()
659 if (DISPLAY_VER(display) >= 10) in ivb_fbc_activate()
669 if (DISPLAY_VER(display) >= 20) in ivb_fbc_activate()
1098 if (DISPLAY_VER(display) >= 9) in rotation_is_valid()
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A Dintel_wm.c165 if (DISPLAY_VER(dev_priv) >= 9) in intel_print_wm_latency()
178 if (DISPLAY_VER(i915) >= 9) in intel_wm_init()
198 if (DISPLAY_VER(dev_priv) >= 9 || in wm_latency_show()
218 if (DISPLAY_VER(dev_priv) >= 9) in pri_wm_latency_show()
233 if (DISPLAY_VER(dev_priv) >= 9) in spr_wm_latency_show()
248 if (DISPLAY_VER(dev_priv) >= 9) in cur_wm_latency_show()
262 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) in pri_wm_latency_open()
329 if (DISPLAY_VER(dev_priv) >= 9) in pri_wm_latency_write()
344 if (DISPLAY_VER(dev_priv) >= 9) in spr_wm_latency_write()
359 if (DISPLAY_VER(dev_priv) >= 9) in cur_wm_latency_write()
A Dintel_psr.c312 if (DISPLAY_VER(display) >= 8) in psr_ctl_reg()
321 if (DISPLAY_VER(display) >= 8) in psr_debug_reg()
330 if (DISPLAY_VER(display) >= 8) in psr_perf_cnt_reg()
339 if (DISPLAY_VER(display) >= 8) in psr_status_reg()
348 if (DISPLAY_VER(display) >= 12) in psr_imr_reg()
357 if (DISPLAY_VER(display) >= 12) in psr_iir_reg()
366 if (DISPLAY_VER(display) >= 8) in psr_aux_ctl_reg()
375 if (DISPLAY_VER(display) >= 8) in psr_aux_data_reg()
1011 if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13) in hsw_activate_psr2()
1018 if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) { in hsw_activate_psr2()
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A Dskl_universal_plane.c754 if (DISPLAY_VER(i915) < 11) in skl_write_plane_wm()
1042 if (DISPLAY_VER(dev_priv) >= 10) in skl_plane_ctl_crtc()
1081 if (DISPLAY_VER(dev_priv) >= 11) in skl_plane_ctl()
1203 if (DISPLAY_VER(i915) < 12) in skl_plane_aux_dist()
1988 if (DISPLAY_VER(i915) >= 13) in skl_check_nv12_aux_surface()
2100 if (DISPLAY_VER(i915) < 11) in check_protection()
2187 if (DISPLAY_VER(i915) >= 20) in skl_plane_has_fbc()
2415 if (DISPLAY_VER(i915) >= 11) in skl_plane_has_rc_ccs()
2428 if (DISPLAY_VER(i915) < 12) in gen12_plane_has_mc_ccs()
2450 if (DISPLAY_VER(i915) < 12) in skl_get_plane_caps()
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A Dintel_display_irq.c190 if (DISPLAY_VER(dev_priv) < 5) in i915_pipestat_enable_mask()
294 if (DISPLAY_VER(dev_priv) >= 4) in i915_enable_asle_pipestat()
384 if (DISPLAY_VER(dev_priv) >= 3) in i9xx_pipe_crc_irq_handler()
808 if (DISPLAY_VER(dev_priv) >= 20) in gen8_de_port_aux_mask()
835 if (DISPLAY_VER(dev_priv) >= 9) in gen8_de_port_aux_mask()
850 if (DISPLAY_VER(dev_priv) >= 14) in gen8_de_pipe_fault_mask()
1023 if (DISPLAY_VER(i915) >= 9) in gen8_de_pipe_flip_done_mask()
1033 if (DISPLAY_VER(dev_priv) >= 13) in gen8_de_pipe_underrun_mask()
1557 if (DISPLAY_VER(dev_priv) >= 14) in gen11_display_irq_reset()
1674 if (DISPLAY_VER(i915) >= 7) { in ilk_de_irq_postinstall()
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A Dintel_alpm.c177 if (DISPLAY_VER(display) < 20) in _lnl_compute_alpm_params()
217 if (DISPLAY_VER(display) >= 12) in io_buffer_wake_time()
239 if (DISPLAY_VER(display) >= 20) in intel_alpm_compute_params()
241 else if (DISPLAY_VER(display) >= 12) in intel_alpm_compute_params()
280 if (DISPLAY_VER(display) < 20) in intel_alpm_lobf_compute_config()
317 if (DISPLAY_VER(display) < 20 || in lnl_alpm_configure()
409 if (DISPLAY_VER(display) < 20 || in intel_alpm_lobf_debugfs_add()
A Dintel_ddi.c212 if (DISPLAY_VER(dev_priv) < 10) { in intel_wait_ddi_buf_active()
217 if (DISPLAY_VER(dev_priv) >= 14) { in intel_wait_ddi_buf_active()
230 if (DISPLAY_VER(dev_priv) >= 14) in intel_wait_ddi_buf_active()
341 if (DISPLAY_VER(i915) >= 14) { in intel_ddi_init_dp_buf_reg()
489 if (DISPLAY_VER(dev_priv) >= 12) in intel_ddi_transcoder_func_reg_val_get()
644 if (DISPLAY_VER(dev_priv) >= 11) in intel_ddi_disable_transcoder_func()
2358 if (DISPLAY_VER(i915) > 20) in intel_ddi_splitter_pipe_mask()
4311 if (DISPLAY_VER(dev_priv) < 9) in intel_ddi_port_sync_transcoders()
4428 if (DISPLAY_VER(i915) >= 14) in intel_ddi_init_dp_connector()
4766 if (DISPLAY_VER(i915) >= 12) in intel_ddi_is_tc()
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A Dintel_fifo_underrun.c196 if (DISPLAY_VER(dev_priv) >= 13) in icl_pipe_status_underrun_mask()
211 if (DISPLAY_VER(dev_priv) >= 11) in bdw_set_fifo_underrun_reporting()
298 else if (DISPLAY_VER(dev_priv) == 7) in __intel_set_cpu_fifo_underrun_reporting()
300 else if (DISPLAY_VER(dev_priv) >= 8) in __intel_set_cpu_fifo_underrun_reporting()
421 if (DISPLAY_VER(dev_priv) >= 11) { in intel_cpu_fifo_underrun_irq_handler()
432 if (DISPLAY_VER(dev_priv) >= 11) in intel_cpu_fifo_underrun_irq_handler()
487 else if (DISPLAY_VER(dev_priv) == 7) in intel_check_cpu_fifo_underruns()
A Dintel_cx0_phy_regs.h40 (DISPLAY_VER(i915__) >= 20 ? \
60 (DISPLAY_VER(i915__) >= 20 ? \
91 (DISPLAY_VER(i915__) >= 20 ? \
116 (DISPLAY_VER(i915__) >= 20 ? \
139 (DISPLAY_VER(i915__) >= 20 ? \
162 (DISPLAY_VER(i915__) >= 20 ? \
179 (DISPLAY_VER(i915__) >= 20 ? \
A Dintel_bw.c156 if (DISPLAY_VER(dev_priv) >= 14) in icl_pcode_restrict_qgv_points()
207 if (DISPLAY_VER(dev_priv) >= 14) in intel_read_qgv_point_info()
225 if (DISPLAY_VER(dev_priv) >= 14) { in icl_get_qgv_points()
490 if (DISPLAY_VER(dev_priv) < 14 && in tgl_get_bw_info()
730 if (DISPLAY_VER(i915) >= 12) in icl_qgv_bw()
790 if (DISPLAY_VER(i915) < 11) in intel_bw_crtc_data_rate()
803 if (DISPLAY_VER(i915) < 12) in intel_bw_crtc_min_cdclk()
1132 if (DISPLAY_VER(i915) >= 14) in intel_bw_check_qgv_points()
1212 if (DISPLAY_VER(i915) < 11) in skl_crtc_calc_dbuf_bw()
1276 if (DISPLAY_VER(dev_priv) < 9) in intel_bw_calc_min_cdclk()
[all …]
A Dintel_sprite_uapi.c13 return DISPLAY_VER(dev_priv) >= 9; in has_dst_key_in_primary_plane()
37 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_PRIMARY && in intel_plane_set_ckey()
76 if (DISPLAY_VER(dev_priv) >= 9 && in intel_sprite_set_colorkey_ioctl()
A Dintel_display_power.c928 if (DISPLAY_VER(dev_priv) >= 20) in get_allowed_dc_mask()
949 DISPLAY_VER(dev_priv) >= 11 ? in get_allowed_dc_mask()
1097 if (DISPLAY_VER(dev_priv) >= 14) in gen9_dbuf_enable()
1111 if (DISPLAY_VER(dev_priv) >= 14) in gen9_dbuf_disable()
1150 if (DISPLAY_VER(dev_priv) == 12) in icl_mbus_init()
1410 if (DISPLAY_VER(dev_priv) >= 14) in intel_pch_reset_handshake()
1912 if (DISPLAY_VER(i915) >= 11) { in intel_power_domains_init_hw()
2100 if (DISPLAY_VER(i915) >= 11) in intel_power_domains_suspend()
2257 if (DISPLAY_VER(i915) >= 11) { in intel_display_power_suspend()
2272 if (DISPLAY_VER(i915) >= 11) { in intel_display_power_resume()
[all …]
A Dintel_display_wa.c36 else if (DISPLAY_VER(i915) == 12) in intel_display_wa_apply()
38 else if (DISPLAY_VER(i915) == 11) in intel_display_wa_apply()
A Dintel_crtc.c113 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in intel_crtc_max_vblank_count()
115 else if (DISPLAY_VER(dev_priv) >= 3) in intel_crtc_max_vblank_count()
311 if (DISPLAY_VER(dev_priv) >= 9) in intel_crtc_init()
326 if (DISPLAY_VER(dev_priv) >= 9) in intel_crtc_init()
348 else if (DISPLAY_VER(dev_priv) == 4) in intel_crtc_init()
352 else if (DISPLAY_VER(dev_priv) == 3) in intel_crtc_init()
357 if (DISPLAY_VER(dev_priv) >= 8) in intel_crtc_init()
369 if (DISPLAY_VER(dev_priv) >= 11) in intel_crtc_init()
621 if (DISPLAY_VER(dev_priv) >= 11 && in intel_pipe_update_end()
A Dintel_dpt_common.c16 if (DISPLAY_VER(i915) == 14) { in intel_dpt_configure()
29 } else if (DISPLAY_VER(i915) == 13) { in intel_dpt_configure()
A Dskl_watermark.c72 return DISPLAY_VER(i915) == 9; in skl_needs_memory_bw_wa()
85 if (DISPLAY_VER(i915) >= 14) { in intel_sagv_block_time()
122 if (DISPLAY_VER(i915) < 11) in intel_sagv_init()
321 if (DISPLAY_VER(i915) >= 11) in intel_sagv_pre_plane_update()
341 if (DISPLAY_VER(i915) >= 11) in intel_sagv_post_plane_update()
427 if (DISPLAY_VER(i915) >= 12) in intel_crtc_can_enable_sagv()
436 if (DISPLAY_VER(i915) < 11 && in intel_can_enable_sagv()
481 DISPLAY_VER(i915) >= 12 && in intel_compute_sagv_mask()
810 if (DISPLAY_VER(i915) >= 11) in skl_ddb_get_hw_plane_state()
2056 if (DISPLAY_VER(i915) == 9) in skl_compute_transition_wm()
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A Dintel_cdclk.c1633 if (DISPLAY_VER(dev_priv) >= 11) in bxt_de_pll_readout()
1650 if (DISPLAY_VER(dev_priv) >= 12) in bxt_get_cdclk()
1699 if (DISPLAY_VER(dev_priv) >= 20) in bxt_get_cdclk()
1897 return DISPLAY_VER(i915) >= 20; in mdclk_source_is_cdclk_pll()
2029 if (DISPLAY_VER(i915) >= 20) in bxt_cdclk_ctl()
2120 if (DISPLAY_VER(dev_priv) >= 14) in bxt_set_cdclk()
2149 if (DISPLAY_VER(dev_priv) >= 11) in bxt_set_cdclk()
2259 else if (DISPLAY_VER(i915) == 9) in intel_cdclk_init_hw()
2274 else if (DISPLAY_VER(i915) == 9) in intel_cdclk_uninit_hw()
2696 if (DISPLAY_VER(dev_priv) >= 10) in intel_pixel_rate_to_cdclk()
[all …]
A Dskl_scaler.c133 if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable && in skl_update_scaler()
177 if (DISPLAY_VER(dev_priv) < 11) { in skl_update_scaler()
182 } else if (DISPLAY_VER(dev_priv) < 12) { in skl_update_scaler()
187 } else if (DISPLAY_VER(dev_priv) < 14) { in skl_update_scaler()
338 if (DISPLAY_VER(dev_priv) >= 11) in skl_update_scaler_plane()
384 if (DISPLAY_VER(dev_priv) == 9) { in intel_atomic_setup_scaler()
402 } else if (DISPLAY_VER(dev_priv) >= 10) { in intel_atomic_setup_scaler()
436 if (DISPLAY_VER(dev_priv) >= 14) { in intel_atomic_setup_scaler()
449 } else if (DISPLAY_VER(dev_priv) >= 10 || in intel_atomic_setup_scaler()
573 if (DISPLAY_VER(dev_priv) >= 10) in intel_atomic_setup_scalers()
A Dintel_display.c308 if (DISPLAY_VER(dev_priv) >= 4) { in intel_wait_for_pipe_off()
443 if (DISPLAY_VER(dev_priv) == 13) in intel_enable_transcoder()
527 if (DISPLAY_VER(dev_priv) >= 12) in intel_disable_transcoder()
877 if (DISPLAY_VER(dev_priv) == 9) in needs_nv12_wa()
910 if (DISPLAY_VER(i915) == 9) { in intel_async_flip_vtd_wa()
1748 if (DISPLAY_VER(dev_priv) < 9) in hsw_crtc_enable()
2497 if (DISPLAY_VER(i915) < 4) { in intel_crtc_compute_pipe_mode()
3104 if (DISPLAY_VER(dev_priv) < 4) in i9xx_get_pipe_config()
3511 if (DISPLAY_VER(i915) >= 12) in joiner_pipes()
3619 if (DISPLAY_VER(i915) >= 11) in hsw_panel_transcoders()
[all …]
A Dintel_pipe_crc.c406 if (DISPLAY_VER(dev_priv) == 2) in get_new_crc_ctl_reg()
408 else if (DISPLAY_VER(dev_priv) < 5) in get_new_crc_ctl_reg()
414 else if (DISPLAY_VER(dev_priv) < 9) in get_new_crc_ctl_reg()
536 if (DISPLAY_VER(dev_priv) == 2) in intel_is_valid_crc_source()
538 else if (DISPLAY_VER(dev_priv) < 5) in intel_is_valid_crc_source()
544 else if (DISPLAY_VER(dev_priv) < 9) in intel_is_valid_crc_source()
A Dintel_dp_aux.c24 if (DISPLAY_VER(display) >= 13 && aux_ch >= AUX_CH_D_XELPD) in aux_ch_name()
26 else if (DISPLAY_VER(display) >= 12 && aux_ch >= AUX_CH_USBC1) in aux_ch_name()
232 if (DISPLAY_VER(display) >= 14) in skl_get_aux_send_ctl()
782 if (DISPLAY_VER(display) >= 14) { in intel_dp_aux_init()
785 } else if (DISPLAY_VER(display) >= 12) { in intel_dp_aux_init()
788 } else if (DISPLAY_VER(display) >= 9) { in intel_dp_aux_init()
802 if (DISPLAY_VER(display) >= 9) in intel_dp_aux_init()
811 if (DISPLAY_VER(display) >= 9) in intel_dp_aux_init()
833 if (DISPLAY_VER(display) == 9 && encoder->port == PORT_E) in default_aux_ch()
A Dintel_dmc.c197 } else if (DISPLAY_VER(i915) == 11) { in dmc_firmware_default()
425 if (DISPLAY_VER(i915) < 12) in disable_all_event_handlers()
475 if (DISPLAY_VER(i915) >= 14 && enable) in pipedmc_clock_gating_wa()
477 else if (DISPLAY_VER(i915) == 13) in pipedmc_clock_gating_wa()
488 if (DISPLAY_VER(i915) >= 14) in intel_dmc_enable_pipe()
501 if (DISPLAY_VER(i915) >= 14) in intel_dmc_disable_pipe()
716 } else if (DISPLAY_VER(i915) >= 13) { in dmc_mmio_addr_sanity_check()
719 } else if (DISPLAY_VER(i915) >= 12) { in dmc_mmio_addr_sanity_check()
1221 str_yes_no(DISPLAY_VER(i915) >= 12)); in intel_dmc_debugfs_status_show()
1226 DISPLAY_VER(i915) >= 14)); in intel_dmc_debugfs_status_show()
[all …]
A Dintel_audio.c505 if (DISPLAY_VER(i915) < 11) in enable_audio_dsc_wa()
510 if (DISPLAY_VER(i915) == 11) in enable_audio_dsc_wa()
512 else if (DISPLAY_VER(i915) >= 12) in enable_audio_dsc_wa()
889 else if (IS_HASWELL(i915) || DISPLAY_VER(i915) >= 8) in intel_audio_hooks_init()
900 if (DISPLAY_VER(i915) >= 13) in intel_audio_cdclk_change_pre()
914 if (DISPLAY_VER(i915) >= 13) { in intel_audio_cdclk_change_post()
993 if (DISPLAY_VER(i915) >= 9) { in i915_audio_component_get_power()
1005 if (DISPLAY_VER(i915) >= 10) in i915_audio_component_get_power()
1034 if (DISPLAY_VER(i915) < 9) in i915_audio_component_codec_wake_override()
1280 if (DISPLAY_VER(i915) >= 9) { in i915_audio_component_init()
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