| /linux/Documentation/devicetree/bindings/clock/ti/ |
| A D | dpll.txt | 1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
10 for the actual DPLL clock.
37 - reg : offsets for the register set for controlling the DPLL.
43 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
45 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
56 - ti,lock : DPLL locks in programmed rate
57 - ti,min-div : the minimum divisor to start from to round the DPLL
59 - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
61 - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
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| A D | apll.txt | 9 a subtype of a DPLL [2], although a simplified one at that.
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| /linux/drivers/dpll/ |
| A D | Kconfig | 3 # Generic DPLL drivers configuration
6 config DPLL config
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | microchip,sparx5-dpll.yaml | 7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
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| /linux/drivers/gpu/drm/i915/display/ |
| A D | intel_dpll.c | 1847 intel_de_write(dev_priv, DPLL(dev_priv, pipe), in i9xx_enable_pll()
1852 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i9xx_enable_pll()
1870 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i9xx_enable_pll()
1999 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in _vlv_enable_pll()
2020 intel_de_write(dev_priv, DPLL(dev_priv, pipe), in vlv_enable_pll()
2167 intel_de_write(dev_priv, DPLL(dev_priv, pipe), in chv_enable_pll()
2252 intel_de_write(dev_priv, DPLL(dev_priv, pipe), val); in vlv_disable_pll()
2253 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in vlv_disable_pll()
2270 intel_de_write(dev_priv, DPLL(dev_priv, pipe), val); in chv_disable_pll()
2271 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in chv_disable_pll()
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| A D | intel_dvo.c | 459 dpll[pipe] = intel_de_rmw(dev_priv, DPLL(dev_priv, pipe), 0, in intel_dvo_init_dev()
466 intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll[pipe]); in intel_dvo_init_dev()
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| A D | intel_display_power_well.c | 1204 u32 val = intel_de_read(dev_priv, DPLL(dev_priv, pipe)); in vlv_display_power_well_init()
1210 intel_de_write(dev_priv, DPLL(dev_priv, pipe), val); in vlv_display_power_well_init()
1365 (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
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| A D | intel_display.c | 388 dpll_reg = DPLL(dev_priv, 0); in vlv_wait_port_ready()
392 dpll_reg = DPLL(dev_priv, 0); in vlv_wait_port_ready()
8311 intel_de_write(dev_priv, DPLL(dev_priv, pipe), in i830_enable_pipe()
8313 intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); in i830_enable_pipe()
8316 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i830_enable_pipe()
8324 intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); in i830_enable_pipe()
8328 intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); in i830_enable_pipe()
8329 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i830_enable_pipe()
8362 intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS); in i830_disable_pipe()
8363 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i830_disable_pipe()
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| A D | intel_pps.c | 128 pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
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| A D | intel_display_power.c | 1771 u32 status = intel_de_read(dev_priv, DPLL(dev_priv, PIPE_A)); in chv_phy_control_init()
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| /linux/include/dt-bindings/clock/ |
| A D | xlnx-zynqmp-clk.h | 15 #define DPLL 3 macro
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| /linux/arch/arm/mach-omap2/ |
| A D | sleep24xx.S | 60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
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| /linux/drivers/net/ethernet/mellanox/mlx5/core/ |
| A D | Kconfig | 204 tristate "Mellanox 5th generation network adapters (ConnectX series) DPLL support"
206 select DPLL
208 DPLL support in Mellanox Technologies ConnectX NICs.
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| /linux/arch/arm/boot/dts/samsung/ |
| A D | exynos5422-odroid-core.dtsi | 101 /* derived from 600MHz DPLL */
203 /* derived from 600MHz DPLL */
239 /* derived from 600MHz DPLL */
251 /* derived from 600MHz DPLL */
266 /* derived from 600MHz DPLL */
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| /linux/Documentation/netlink/specs/ |
| A D | dpll.yaml | 5 doc: DPLL subsystem.
424 Get list of DPLL devices (dump) or attributes of a single dpll device
451 doc: Set attributes for a DPLL device
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| /linux/Documentation/devicetree/bindings/phy/ |
| A D | ti-phy.txt | 10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
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| /linux/Documentation/driver-api/ |
| A D | dpll.rst | 7 DPLL chapter
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
17 DPLL's input and output may be configurable.
160 pick a highest priority valid signal and use it to control the DPLL
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| /linux/Documentation/arch/arm/omap/ |
| A D | dss.rst | 32 - Use DSI DPLL to create DSS FCK
301 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
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| /linux/drivers/ptp/ |
| A D | Kconfig | 203 select DPLL
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| /linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
| A D | reg.h | 256 #define DPLL 0x034A macro
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| /linux/drivers/net/ethernet/intel/ |
| A D | Kconfig | 295 select DPLL
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| /linux/arch/arm/boot/dts/rockchip/ |
| A D | rk3036.dtsi | 238 * Fix the emac parent clock is DPLL instead of APLL.
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| /linux/Documentation/networking/device_drivers/hamradio/ |
| A D | z8530drv.rst | 308 present at all (BayCom). It feeds back the output of the DPLL
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| /linux/drivers/gpu/drm/i915/ |
| A D | i915_reg.h | 671 #define DPLL(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ macro
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| /linux/ |
| A D | MAINTAINERS | 6920 DPLL SUBSYSTEM
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