Searched refs:DRRDisplay (Results 1 – 10 of 10) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_mode_vba_util_32.h | 591 bool DRRDisplay[],
684 bool DRRDisplay,
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| A D | display_mode_vba_util_32.c | 2921 bool DRRDisplay[], in dml32_UseMinimumDCFCLK() argument
3045 DRRDisplay[k], in dml32_UseMinimumDCFCLK()
3248 bool DRRDisplay, in dml32_CalculateTWait() argument
3260 !(SynchronizeDRRDisplaysForUCLKPStateChangeFinal && DRRDisplay)) { in dml32_CalculateTWait()
4499 (v->DRRDisplay[i] || v->DRRDisplay[j]))) { in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
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| A D | display_mode_vba_32.c | 756 mode_lib->vba.DRRDisplay[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3056 mode_lib->vba.DRRDisplay, in dml32_ModeSupportAndSystemConfigurationFull()
3262 mode_lib->vba.DRRDisplay[k], in dml32_ModeSupportAndSystemConfigurationFull()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_utils.c | 46 dml_timing_array->DRRDisplay[dst_index] = dml_timing_array->DRRDisplay[src_index]; in dml2_util_copy_dml_timing()
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| A D | display_mode_core_structs.h | 557 dml_bool_t DRRDisplay[__DML_NUM_PLANES__]; member
1216 dml_bool_t *DRRDisplay; member
1283 dml_bool_t *DRRDisplay; member
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| A D | dml2_translation_helper.c | 732 out->DRRDisplay[location] = false; in populate_dml_timing_cfg_from_stream_state()
1157 dml_dispcfg->timing.DRRDisplay[0] = true; in apply_legacy_svp_drr_settings()
1162 dml_dispcfg->timing.DRRDisplay[i] = true; in apply_legacy_svp_drr_settings()
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| A D | display_mode_core.c | 279 dml_bool_t DRRDisplay,
1742 dml_bool_t DRRDisplay, in CalculateTWait() argument
2981 (p->SynchronizeDRRDisplaysForUCLKPStateChangeFinal && (p->DRRDisplay[i] || p->DRRDisplay[j]))) { in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
2995 …eSupportNumber = ((p->SynchronizeDRRDisplaysForUCLKPStateChangeFinal && p->DRRDisplay[k]) ? 2 : 1); in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3026 …geSupportNumber = (p->SynchronizeDRRDisplaysForUCLKPStateChangeFinal && p->DRRDisplay[k]) ? 2 : 1; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
4633 p->DRRDisplay[k], in UseMinimumDCFCLK()
6355 mode_lib->ms.cache_display_cfg.timing.DRRDisplay[k], in dml_prefetch_check()
6656 CalculateWatermarks_params->DRRDisplay = mode_lib->ms.cache_display_cfg.timing.DRRDisplay; in dml_prefetch_check()
7953 UseMinimumDCFCLK_params->DRRDisplay = mode_lib->ms.cache_display_cfg.timing.DRRDisplay; in dml_core_mode_support()
8953 mode_lib->ms.cache_display_cfg.timing.DRRDisplay[k], in dml_core_mode_programming()
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| A D | display_mode_util.c | 539 dml_print("DML: timing_cfg: plane=%d, DRRDisplay = %d\n", i, timing->DRRDisplay[i]); in dml_print_dml_display_cfg_timing()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_vba.h | 452 bool DRRDisplay[DC__NUM_DPP__MAX]; member
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| A D | display_mode_vba.c | 708 mode_lib->vba.DRRDisplay[mode_lib->vba.NumberOfActiveSurfaces] = dst->drr_display; in fetch_pipe_params()
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