Searched refs:DSPCNTR (Results 1 – 10 of 10) sorted by relevance
| /linux/drivers/gpu/drm/i915/display/ |
| A D | i9xx_plane.c | 500 intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); in i9xx_plane_update_arm()
543 intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); in i9xx_plane_disable_arm()
565 intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); in g4x_primary_async_flip()
689 val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); in i9xx_plane_get_hw_state()
1085 val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); in i9xx_get_initial_plane_config()
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| A D | i9xx_plane_regs.h | 15 #define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) macro
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| A D | intel_display.c | 8347 intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_A)) & DISP_ENABLE); in i830_disable_pipe()
8349 intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_B)) & DISP_ENABLE); in i830_disable_pipe()
8351 intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_C)) & DISP_ENABLE); in i830_disable_pipe()
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| A D | intel_color.c | 1042 tmp = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); in i9xx_get_config()
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| /linux/drivers/gpu/drm/i915/gvt/ |
| A D | display.c | 196 vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
510 vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE; in emulate_monitor_status_change()
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| A D | fb_decoder.c | 220 val = vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)); in intel_vgpu_decode_primary_plane()
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| A D | cmd_parser.c | 1318 info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); in gen8_decode_mi_display_flip()
1384 info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); in skl_decode_mi_display_flip()
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| A D | handlers.c | 1027 if (vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) & PLANE_CTL_ASYNC_FLIP) in pri_surf_mmio_write()
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| /linux/drivers/gpu/drm/i915/ |
| A D | intel_gvt_mmio_table.c | 168 MMIO_D(DSPCNTR(dev_priv, PIPE_A)); in iterate_generic_mmio()
177 MMIO_D(DSPCNTR(dev_priv, PIPE_B)); in iterate_generic_mmio()
186 MMIO_D(DSPCNTR(dev_priv, PIPE_C)); in iterate_generic_mmio()
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| A D | intel_clock_gating.c | 137 intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(dev_priv, pipe), in g4x_disable_trickle_feed()
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