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Searched refs:DSSERR (Results 1 – 25 of 39) sorted by relevance

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/linux/drivers/video/fbdev/omap2/omapfb/dss/
A Doverlay.c84 DSSERR("failed to create sysfs file\n"); in dss_init_overlays()
107 DSSERR("check_overlay: overlay %d doesn't support " in dss_ovl_simple_check()
113 DSSERR("check_overlay: overlay %d doesn't support " in dss_ovl_simple_check()
120 DSSERR("check_overlay: overlay %d doesn't support mode %d\n", in dss_ovl_simple_check()
126 DSSERR("check_overlay: zorder %d too high\n", info->zorder); in dss_ovl_simple_check()
131 DSSERR("check_overlay: rotation type %d not supported\n", in dss_ovl_simple_check()
164 DSSERR("overlay %d horizontally not inside the display area " in dss_ovl_check()
171 DSSERR("overlay %d vertically not inside the display area " in dss_ovl_check()
A Ddispc-compat.c387 DSSERR("OCP_ERR\n"); in dispc_error_worker()
439 DSSERR("dispc_request_irq failed\n"); in dss_dispc_initialize_irq()
481 DSSERR("failed to register FRAMEDONE isr\n"); in dispc_mgr_disable_lcd_out()
493 DSSERR("timeout waiting for FRAME DONE\n"); in dispc_mgr_disable_lcd_out()
498 DSSERR("failed to unregister FRAMEDONE isr\n"); in dispc_mgr_disable_lcd_out()
531 DSSERR("failed to register %x isr\n", irq_mask); in dispc_mgr_enable_digit_out()
539 DSSERR("timeout waiting for digit out to start\n"); in dispc_mgr_enable_digit_out()
544 DSSERR("failed to unregister %x isr\n", irq_mask); in dispc_mgr_enable_digit_out()
584 DSSERR("failed to register %x isr\n", irq_mask); in dispc_mgr_disable_digit_out()
597 DSSERR("timeout waiting for digit out to stop\n"); in dispc_mgr_disable_digit_out()
[all …]
A Ddsi.c2528 DSSERR("\t\tSoT Error\n"); in dsi_show_rx_ack_with_err()
2530 DSSERR("\t\tSoT Sync Error\n"); in dsi_show_rx_ack_with_err()
2532 DSSERR("\t\tEoT Sync Error\n"); in dsi_show_rx_ack_with_err()
2542 DSSERR("\t\t(reserved7)\n"); in dsi_show_rx_ack_with_err()
2548 DSSERR("\t\tChecksum Error\n"); in dsi_show_rx_ack_with_err()
2552 DSSERR("\t\tInvalid VC ID\n"); in dsi_show_rx_ack_with_err()
2556 DSSERR("\t\t(reserved14)\n"); in dsi_show_rx_ack_with_err()
4914 DSSERR("VC ID out of range\n"); in dsi_set_vc_id()
4954 DSSERR("can't get fck\n"); in dsi_get_clocks()
5218 DSSERR("can't get sys_clk\n"); in dsi_init_pll_data()
[all …]
A Dapply.c516 DSSERR("mgr(%d)->wait_for_go() not finishing\n", in dss_mgr_wait_for_go()
527 DSSERR("mgr(%d)->wait_for_go() timeout\n", mgr->id); in dss_mgr_wait_for_go()
593 DSSERR("ovl(%d)->wait_for_go() not finishing\n", in dss_mgr_wait_for_go_ovl()
604 DSSERR("ovl(%d)->wait_for_go() timeout\n", ovl->id); in dss_mgr_wait_for_go_ovl()
639 DSSERR("dispc_ovl_setup failed for ovl %d\n", ovl->id); in dss_ovl_write_regs()
740 DSSERR("cannot write registers for manager %s: " in dss_write_regs()
1187 DSSERR("output does not support manager %s\n", in dss_mgr_set_output()
1213 DSSERR("failed to unset output, output not set\n"); in dss_mgr_unset_output()
1345 DSSERR("overlay '%s' already has a manager '%s'\n", in dss_ovl_set_manager()
1393 DSSERR("failed to detach overlay: manager not set\n"); in dss_ovl_unset_manager()
[all …]
A Dhdmi4.c101 DSSERR("can't get VDDA regulator\n"); in hdmi_init_regulator()
167 DSSERR("Failed to enable PLL\n"); in hdmi_power_on_full()
173 DSSERR("Failed to configure PLL\n"); in hdmi_power_on_full()
326 DSSERR("failed to enable display: no output/manager\n"); in hdmi_display_enable()
333 DSSERR("failed to power on device\n"); in hdmi_display_enable()
341 DSSERR("Error restoring audio configuration: %d", r); in hdmi_display_enable()
389 DSSERR("failed to power on device\n"); in hdmi_core_enable()
432 DSSERR("failed to connect output to new device: %s\n", in hdmi_connect()
703 DSSERR("platform_get_irq failed\n"); in hdmi4_bind()
712 DSSERR("HDMI IRQ request failed\n"); in hdmi4_bind()
[all …]
A Dhdmi5.c118 DSSERR("can't get VDDA regulator\n"); in hdmi_init_regulator()
184 DSSERR("Failed to enable PLL\n"); in hdmi_power_on_full()
190 DSSERR("Failed to configure PLL\n"); in hdmi_power_on_full()
356 DSSERR("failed to enable display: no output/manager\n"); in hdmi_display_enable()
363 DSSERR("failed to power on device\n"); in hdmi_display_enable()
371 DSSERR("Error restoring audio configuration: %d", r); in hdmi_display_enable()
419 DSSERR("failed to power on device\n"); in hdmi_core_enable()
462 DSSERR("failed to connect output to new device: %s\n", in hdmi_connect()
744 DSSERR("platform_get_irq failed\n"); in hdmi5_bind()
753 DSSERR("HDMI IRQ request failed\n"); in hdmi5_bind()
[all …]
A Dmanager.c81 DSSERR("failed to create sysfs file\n"); in dss_init_overlay_managers_sysfs()
131 DSSERR("check_manager: illegal transparency key\n"); in dss_mgr_simple_check()
161 DSSERR("overlays %d and %d have the same " in dss_mgr_check_zorder()
176 DSSERR("check_manager: invalid timings\n"); in dss_mgr_check_timings()
A Ddss.c187 DSSERR("illegal DSS PLL ID %d\n", pll_id); in dss_ctrl_pll_enable()
213 DSSERR("error in PLL mux config for LCD\n"); in dss_ctrl_pll_set_control_mux()
229 DSSERR("error in PLL mux config for LCD2\n"); in dss_ctrl_pll_set_control_mux()
251 DSSERR("error in PLL mux config\n"); in dss_ctrl_pll_set_control_mux()
295 DSSERR("PLL lock request timed out\n"); in dss_sdi_enable()
307 DSSERR("PLL lock timed out\n"); in dss_sdi_enable()
318 DSSERR("SDI reset timed out\n"); in dss_sdi_enable()
737 DSSERR("can't get clock fck\n"); in dss_get_clocks()
1045 DSSERR("can't get DPLL VDDA regulator\n"); in dss_video_pll_probe()
1083 DSSERR("can't get IORESOURCE_MEM DSS\n"); in dss_bind()
[all …]
A Doutput.c28 DSSERR("output already has device %s connected to it\n", in omapdss_output_set_device()
35 DSSERR("output type and display type don't match\n"); in omapdss_output_set_device()
60 DSSERR("output doesn't have a device connected to it\n"); in omapdss_output_unset_device()
66 DSSERR("device %s is not disabled, cannot unset device\n", in omapdss_output_unset_device()
A Dhdmi_wp.c80 DSSERR("Failed to set PHY power mode to %d\n", val); in hdmi_wp_set_phy_pwr()
96 DSSERR("Failed to set PLL_PWR_STATUS\n"); in hdmi_wp_set_pll_pwr()
128 DSSERR("no HDMI FRAMEDONE when disabling output\n"); in hdmi_wp_video_stop()
264 DSSERR("can't get WP mem resource\n"); in hdmi_wp_init()
271 DSSERR("can't ioremap HDMI WP\n"); in hdmi_wp_init()
A Dhdmi4_core.c50 DSSERR("Timeout aborting DDC transaction\n"); in hdmi_core_ddc_init()
61 DSSERR("Timeout starting SCL clock\n"); in hdmi_core_ddc_init()
71 DSSERR("Timeout clearing DDC fifo\n"); in hdmi_core_ddc_init()
89 DSSERR("Timeout waiting DDC to be ready\n"); in hdmi_core_ddc_edid()
117 DSSERR("I2C Bus Low?\n"); in hdmi_core_ddc_edid()
122 DSSERR("I2C No Ack\n"); in hdmi_core_ddc_edid()
131 DSSERR("operation stopped when reading edid\n"); in hdmi_core_ddc_edid()
139 DSSERR("timeout reading edid\n"); in hdmi_core_ddc_edid()
153 DSSERR("E-EDID checksum failed!!\n"); in hdmi_core_ddc_edid()
880 DSSERR("can't ioremap CORE\n"); in hdmi4_core_init()
A Dmanager-sysfs.c66 DSSERR("new display is already connected\n"); in manager_display_store()
72 DSSERR("new display is not disabled\n"); in manager_display_store()
81 DSSERR("old display is not disabled\n"); in manager_display_store()
92 DSSERR("failed to connect new device\n"); in manager_display_store()
98 DSSERR("failed to connect device to this manager\n"); in manager_display_store()
105 DSSERR("failed to apply dispc config\n"); in manager_display_store()
A Dvenc.c333 DSSERR("Failed to reset venc\n"); in venc_reset()
455 DSSERR("Failed to enable display: no output/manager\n"); in venc_display_enable()
596 DSSERR("can't get VDDA_DAC regulator\n"); in venc_init_regulator()
666 DSSERR("can't get tv_dac_clk\n"); in venc_get_clocks()
698 DSSERR("failed to connect output to new device: %s\n", in venc_connect()
819 DSSERR("can't get IORESOURCE_MEM VENC\n"); in venc_bind()
826 DSSERR("can't ioremap VENC\n"); in venc_bind()
848 DSSERR("Invalid DT data\n"); in venc_bind()
A Dpll.c296 DSSERR("DSS DPLL GO bit not going down.\n"); in dss_pll_write_config_type_a()
302 DSSERR("cannot lock DSS DPLL\n"); in dss_pll_write_config_type_a()
322 DSSERR("failed to enable HSDIV clocks\n"); in dss_pll_write_config_type_a()
368 DSSERR("DSS DPLL GO bit not going down.\n"); in dss_pll_write_config_type_b()
373 DSSERR("cannot lock DSS DPLL\n"); in dss_pll_write_config_type_b()
A Dhdmi_pll.c179 DSSERR("can't get sys_clk\n"); in dsi_init_pll_data()
217 DSSERR("can't ioremap PLLCTRL\n"); in hdmi_pll_init()
223 DSSERR("failed to init HDMI PLL\n"); in hdmi_pll_init()
A Dsdi.c129 DSSERR("failed to enable display: no output/manager\n"); in sdi_display_enable()
260 DSSERR("can't get VDDS_SDI regulator\n"); in sdi_init_regulator()
289 DSSERR("failed to connect output to new device: %s\n", in sdi_connect()
414 DSSERR("failed to parse datapairs\n"); in sdi_init_port()
A Ddpi.c382 DSSERR("no VDSS_DSI regulator\n"); in dpi_display_enable()
388 DSSERR("failed to enable display: no output/manager\n"); in dpi_display_enable()
574 DSSERR("can't get VDDS_DSI regulator\n"); in dpi_init_regulator()
671 DSSERR("failed to connect output to new device: %s\n", in dpi_connect()
854 DSSERR("failed to parse datalines\n"); in dpi_init_port()
/linux/drivers/gpu/drm/omapdrm/dss/
A Ddsi.c1936 DSSERR("\t\tSoT Error\n"); in dsi_show_rx_ack_with_err()
1938 DSSERR("\t\tSoT Sync Error\n"); in dsi_show_rx_ack_with_err()
1940 DSSERR("\t\tEoT Sync Error\n"); in dsi_show_rx_ack_with_err()
1950 DSSERR("\t\t(reserved7)\n"); in dsi_show_rx_ack_with_err()
1956 DSSERR("\t\tChecksum Error\n"); in dsi_show_rx_ack_with_err()
1960 DSSERR("\t\tInvalid VC ID\n"); in dsi_show_rx_ack_with_err()
1964 DSSERR("\t\t(reserved14)\n"); in dsi_show_rx_ack_with_err()
1976 DSSERR("\trawval %#08x\n", val); in dsi_vc_flush_receive_data()
2217 DSSERR("bta sync failed\n"); in dsi_vc_write_common()
4264 DSSERR("can't get fck\n"); in dsi_get_clocks()
[all …]
A Dhdmi5.c178 DSSERR("Failed to enable PLL\n"); in hdmi_power_on_full()
184 DSSERR("Failed to configure PLL\n"); in hdmi_power_on_full()
287 DSSERR("failed to power on device\n"); in hdmi_core_enable()
385 DSSERR("failed to power on device\n"); in hdmi5_bridge_enable()
394 DSSERR("Error restoring audio configuration: %d", ret); in hdmi5_bridge_enable()
538 DSSERR("%s: Video mode does not support audio\n", in hdmi_audio_start()
554 DSSERR("%s: Video mode does not support audio\n", __func__); in hdmi_audio_stop()
638 DSSERR("Registering HDMI audio failed %d\n", r); in hdmi5_bind()
759 DSSERR("platform_get_irq failed\n"); in hdmi5_probe()
768 DSSERR("HDMI IRQ request failed\n"); in hdmi5_probe()
[all …]
A Dhdmi4.c179 DSSERR("Failed to enable PLL\n"); in hdmi_power_on_full()
185 DSSERR("Failed to configure PLL\n"); in hdmi_power_on_full()
287 DSSERR("failed to power on device\n"); in hdmi4_core_enable()
387 DSSERR("failed to power on device\n"); in hdmi4_bridge_enable()
396 DSSERR("Error restoring audio configuration: %d", ret); in hdmi4_bridge_enable()
563 DSSERR("%s: Video mode does not support audio\n", in hdmi_audio_start()
665 DSSERR("Registering HDMI audio failed\n"); in hdmi4_bind()
793 DSSERR("platform_get_irq failed\n"); in hdmi4_probe()
802 DSSERR("HDMI IRQ request failed\n"); in hdmi4_probe()
810 DSSERR("can't get VDDA regulator\n"); in hdmi4_probe()
A Dpll.c481 DSSERR("cannot lock PLL\n"); in dss_pll_write_config_type_a()
489 DSSERR("DSS DPLL GO bit not going down.\n"); in dss_pll_write_config_type_a()
495 DSSERR("cannot lock DSS DPLL\n"); in dss_pll_write_config_type_a()
516 DSSERR("failed to enable HSDIV clocks\n"); in dss_pll_write_config_type_a()
562 DSSERR("DSS DPLL GO bit not going down.\n"); in dss_pll_write_config_type_b()
567 DSSERR("cannot lock DSS DPLL\n"); in dss_pll_write_config_type_b()
A Dhdmi4_core.c49 DSSERR("Timeout aborting DDC transaction\n"); in hdmi4_core_ddc_init()
60 DSSERR("Timeout starting SCL clock\n"); in hdmi4_core_ddc_init()
70 DSSERR("Timeout clearing DDC fifo\n"); in hdmi4_core_ddc_init()
86 DSSERR("Timeout waiting DDC to be ready\n"); in hdmi4_core_ddc_read()
111 DSSERR("I2C Bus Low?\n"); in hdmi4_core_ddc_read()
116 DSSERR("I2C No Ack\n"); in hdmi4_core_ddc_read()
125 DSSERR("operation stopped when reading edid\n"); in hdmi4_core_ddc_read()
133 DSSERR("timeout reading edid\n"); in hdmi4_core_ddc_read()
A Ddss.c168 DSSERR("illegal DSS PLL ID %d\n", pll->id); in dss_ctrl_pll_enable()
196 DSSERR("error in PLL mux config for LCD\n"); in dss_ctrl_pll_set_control_mux()
212 DSSERR("error in PLL mux config for LCD2\n"); in dss_ctrl_pll_set_control_mux()
228 DSSERR("error in PLL mux config for LCD3\n"); in dss_ctrl_pll_set_control_mux()
234 DSSERR("error in PLL mux config\n"); in dss_ctrl_pll_set_control_mux()
280 DSSERR("PLL lock request timed out\n"); in dss_sdi_enable()
292 DSSERR("PLL lock timed out\n"); in dss_sdi_enable()
303 DSSERR("SDI reset timed out\n"); in dss_sdi_enable()
827 DSSERR("can't get clock fck\n"); in dss_get_clocks()
836 DSSERR("Failed to get %s\n", in dss_get_clocks()
[all …]
A Dhdmi_pll.c138 DSSERR("can't get sys_clk\n"); in hdmi_init_pll_data()
175 DSSERR("failed to init HDMI PLL\n"); in hdmi_pll_init()
A Dhdmi_wp.c79 DSSERR("Failed to set PHY power mode to %d\n", val); in hdmi_wp_set_phy_pwr()
95 DSSERR("Failed to set PLL_PWR_STATUS\n"); in hdmi_wp_set_pll_pwr()
127 DSSERR("no HDMI FRAMEDONE when disabling output\n"); in hdmi_wp_video_stop()

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