Searched refs:GCC_VIDEO_AXI1_CLK_ARES (Results 1 – 14 of 14) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| A D | qcom,gcc-sm8450.h | 234 #define GCC_VIDEO_AXI1_CLK_ARES 35 macro
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| A D | qcom,sm8550-gcc.h | 218 #define GCC_VIDEO_AXI1_CLK_ARES 34 macro
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| A D | qcom,sm8650-gcc.h | 241 #define GCC_VIDEO_AXI1_CLK_ARES 34 macro
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| A D | qcom,gcc-sm8250.h | 256 #define GCC_VIDEO_AXI1_CLK_ARES 44 macro
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| A D | qcom,gcc-sm8350.h | 250 #define GCC_VIDEO_AXI1_CLK_ARES 36 macro
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| A D | qcom,sa8775p-gcc.h | 307 #define GCC_VIDEO_AXI1_CLK_ARES 45 macro
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| A D | qcom,gcc-sc8280xp.h | 480 #define GCC_VIDEO_AXI1_CLK_ARES 78 macro
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| /linux/drivers/clk/qcom/ |
| A D | gcc-sm8450.c | 3206 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x42020, .bit = 2, .udelay = 1000 },
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| A D | gcc-sm8550.c | 3280 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 },
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| A D | gcc-sm8250.c | 3580 [GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, .bit = 2, .udelay = 150 },
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| A D | gcc-sm8650.c | 3738 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 },
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| A D | gcc-sm8350.c | 3747 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x28018, .bit = 2, .udelay = 400 },
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| A D | gcc-sa8775p.c | 4599 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x3401c, .bit = 2, .udelay = 400 },
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| A D | gcc-sc8280xp.c | 7452 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x28018, .bit = 2, .udelay = 400 },
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