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Searched refs:GC_HWIP (Results 1 – 25 of 59) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
A Dsoc15_common.h111 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP, 0)
118 …uint32_t r0 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG…
119 …uint32_t r1 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG…
120 …uint32_t spare_int = adev->reg_offset[GC_HWIP][inst][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC…
139 …_((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP, inst)
143 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP, 0)
155 …uint32_t r2 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG…
156 …uint32_t r3 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG…
157 …uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRB…
158 …uint32_t grbm_idx = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRB…
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A Dgmc_v9_0.c648 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) in gmc_v9_0_process_interrupt()
662 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) in gmc_v9_0_process_interrupt()
792 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) in gmc_v9_0_use_invalidate_semaphore()
1140 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v9_0_get_coherence_flags()
1154 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == in gmc_v9_0_get_coherence_flags()
1156 amdgpu_ip_version(adev, GC_HWIP, 0) == in gmc_v9_0_get_coherence_flags()
1727 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v9_0_mc_init()
2046 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v9_0_sw_init()
2138 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= in gmc_v9_0_sw_init()
2328 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && in gmc_v9_0_hw_init()
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A Dgmc_v10_0.c147 (amdgpu_ip_version(adev, GC_HWIP, 0) < in gmc_v10_0_process_interrupt()
281 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; in gmc_v10_0_flush_gpu_tlb()
312 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0))) in gmc_v10_0_flush_gpu_tlb()
615 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_set_gfxhub_funcs()
731 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_mc_init()
798 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_sw_init()
816 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_sw_init()
1127 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 3) || in gmc_v10_0_get_clockgating_state()
1128 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 4)) in gmc_v10_0_get_clockgating_state()
A Damdgpu_discovery.c205 [GC_HWIP] = GC_HWID,
1788 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_set_common_ip_blocks()
1833 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_common_ip_blocks()
1842 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_set_gmc_ip_blocks()
1886 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_gmc_ip_blocks()
2134 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_set_gc_ip_blocks()
2180 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_gc_ip_blocks()
2336 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_set_mes_ip_blocks()
2365 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_init_soc_config()
2605 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_set_ip_blocks()
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A Dgmc_v12_0.c211 GC_HWIP : MMHUB_HWIP; in gmc_v12_0_flush_vm_hub()
549 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) && in gmc_v12_0_get_dcc_alignment()
550 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1)) in gmc_v12_0_get_dcc_alignment()
597 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v12_0_set_gfxhub_funcs()
752 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v12_0_sw_init()
A Dgfx_v9_0.c1071 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_init_golden_registers()
1278 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_check_fw_write_wait()
1395 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_check_if_need_gfxoff()
2015 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_gpu_early_init()
2209 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_sw_init()
2225 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_sw_init()
2593 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_init_sq_config()
3042 if (amdgpu_ip_version(adev, GC_HWIP, 0) == in gfx_v9_0_init_pg()
3156 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_rlc_resume()
4229 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_get_gpu_clock_counter()
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A Damdgpu_display.c795 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) in convert_tiling_flags_to_modifier()
797 else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= in convert_tiling_flags_to_modifier()
800 else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= in convert_tiling_flags_to_modifier()
810 if (amdgpu_ip_version(adev, GC_HWIP, 0) < in convert_tiling_flags_to_modifier()
817 if (amdgpu_ip_version(adev, GC_HWIP, 0) < in convert_tiling_flags_to_modifier()
875 amdgpu_ip_version(adev, GC_HWIP, 0) < in convert_tiling_flags_to_modifier()
913 if ((amdgpu_ip_version(adev, GC_HWIP, in convert_tiling_flags_to_modifier()
1272 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) in amdgpu_display_framebuffer_init()
A Damdgpu_vm.h123 …((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_P…
137 …((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGP…
141 …((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_P…
A Ddimgrey_cavefish_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
A Daldebaran_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in aldebaran_reg_base_init()
A Dgmc_v11_0.c242 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; in gmc_v11_0_flush_gpu_tlb()
589 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_set_gfxhub_funcs()
652 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 5, 0)) && in gmc_v11_0_vram_gtt_location()
750 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_sw_init()
A Darct_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
A Dpsp_v10_0.c61 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 1, 0)) && in psp_v10_0_init_microcode()
A Dgfx_v10_0.c3806 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_init_spm_golden_registers()
3832 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_init_golden_registers()
4056 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_check_fw_write_wait()
4107 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_check_gfxoff_flag()
4304 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_init_rlcg_reg_access_ctrl()
4518 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_gpu_early_init()
4692 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v10_0_sw_init()
4958 if (((amdgpu_ip_version(adev, GC_HWIP, 0) == in gfx_v10_0_setup_rb()
8156 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == in gfx_v10_0_update_gfx_clock_gating()
8158 (amdgpu_ip_version(adev, GC_HWIP, 0) == in gfx_v10_0_update_gfx_clock_gating()
[all …]
A Damdgpu_mes.c1537 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= in amdgpu_mes_self_test()
1539 amdgpu_ip_version(adev, GC_HWIP, 0) < in amdgpu_mes_self_test()
1599 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, in amdgpu_mes_init_microcode()
1604 } else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && in amdgpu_mes_init_microcode()
1605 amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0)) { in amdgpu_mes_init_microcode()
1672 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && in amdgpu_mes_suspend_resume_all_supported()
1673 amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0) && in amdgpu_mes_suspend_resume_all_supported()
A Damdgpu_amdkfd.c581 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)) in amdgpu_amdkfd_get_xgmi_bandwidth_mbytes()
718 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 && in amdgpu_amdkfd_set_compute_idle()
722 } else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) && in amdgpu_amdkfd_set_compute_idle()
A Dvega10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
A Dimu_v11_0.c52 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in imu_v11_0_init_microcode()
356 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in imu_v11_0_program_rlc_ram()
A Dimu_v12_0.c49 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in imu_v12_0_init_microcode()
369 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in imu_v12_0_program_rlc_ram()
A Dgfxhub_v1_2.c366 amdgpu_ip_version(adev, GC_HWIP, 0) == in gfxhub_v1_2_xcc_setup_vmid_config()
368 amdgpu_ip_version(adev, GC_HWIP, 0) == in gfxhub_v1_2_xcc_setup_vmid_config()
370 amdgpu_ip_version(adev, GC_HWIP, 0) == in gfxhub_v1_2_xcc_setup_vmid_config()
A Dvega20_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
A Dsoc24.c263 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc24_need_full_reset()
389 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc24_common_early_init()
A Damdgpu_device.c680 GC_HWIP, false, in amdgpu_device_xcc_rreg()
811 GC_HWIP, true, in amdgpu_device_xcc_wreg()
1310 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || in amdgpu_device_asic_init()
1311 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || in amdgpu_device_asic_init()
1312 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) { in amdgpu_device_asic_init()
3220 if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(9, 0, 0)) in amdgpu_device_smu_fini_early()
4210 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) in amdgpu_device_init()
4234 (amdgpu_ip_version(adev, GC_HWIP, 0) > in amdgpu_device_init()
5101 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || in amdgpu_device_reset_sriov()
5102 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || in amdgpu_device_reset_sriov()
[all …]
A Damdgpu_ucode.c1324 if (amdgpu_ip_version(adev, GC_HWIP, 0) == in amdgpu_ucode_legacy_naming()
1337 } else if (block_type == GC_HWIP) { in amdgpu_ucode_legacy_naming()
1338 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_ucode_legacy_naming()
1400 case GC_HWIP: in amdgpu_ucode_ip_version_decode()
/linux/drivers/gpu/drm/amd/amdkfd/
A Dkfd_int_process_v9.c170 if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { in event_interrupt_poison_consumption_v9()
177 } else if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { in event_interrupt_poison_consumption_v9()

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