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Searched refs:GET_INST (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dgfxhub_v1_2.c92 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
95 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
99 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
102 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
106 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
109 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
113 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
116 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
295 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_disable_identity_aperture()
298 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_disable_identity_aperture()
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A Dgfx_v9_4_3.c348 dev_inst = GET_INST(GC, i); in gfx_v9_4_3_init_golden_registers()
2001 GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_kiq_init_register()
2007 GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_kiq_init_register()
2335 GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_fini()
4421 GET_INST(GC, xcc_id), in gfx_v9_4_3_inst_query_ras_err_count()
4430 GET_INST(GC, xcc_id), in gfx_v9_4_3_inst_query_ras_err_count()
4451 GET_INST(GC, xcc_id), in gfx_v9_4_3_inst_query_ras_err_count()
4487 GET_INST(GC, xcc_id)); in gfx_v9_4_3_inst_reset_ras_err_count()
4492 GET_INST(GC, xcc_id)); in gfx_v9_4_3_inst_reset_ras_err_count()
4509 GET_INST(GC, xcc_id)); in gfx_v9_4_3_inst_reset_ras_err_count()
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A Damdgpu_amdkfd_gfx_v9.c59 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_unlock_srbm()
171 WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL, in kgd_gfx_v9_init_interrupts()
636 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, sq_cmd); in kgd_gfx_v9_wave_control_execute()
909 *wait_times = RREG32_SOC15_RLC(GC, GET_INST(GC, inst), in kgd_gfx_v9_get_iq_wait_times()
1036 soc15_grbm_select(adev, 1, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_get_cu_occupancy()
1074 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_get_cu_occupancy()
1113 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_LO, in kgd_gfx_v9_program_trap_handler_settings()
1115 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_HI, in kgd_gfx_v9_program_trap_handler_settings()
1121 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_LO, in kgd_gfx_v9_program_trap_handler_settings()
1123 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_HI, in kgd_gfx_v9_program_trap_handler_settings()
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A Damdgpu_jpeg.h38 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
41 JPEG, GET_INST(JPEG, inst_idx), \
65 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
67 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
70 JPEG, GET_INST(JPEG, inst_idx), \
79 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
81 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
A Damdgpu_amdkfd_gc_9_4_3.c48 SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id), in get_sdma_rlc_reg_offset()
228 unsigned int phy_inst = GET_INST(GC, xcc_inst); in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
299 hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR); in kgd_gfx_v9_4_3_hqd_load()
338 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO, in kgd_gfx_v9_4_3_hqd_load()
340 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI, in kgd_gfx_v9_4_3_hqd_load()
342 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR, in kgd_gfx_v9_4_3_hqd_load()
346 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1, in kgd_gfx_v9_4_3_hqd_load()
351 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR, in kgd_gfx_v9_4_3_hqd_load()
355 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data); in kgd_gfx_v9_4_3_hqd_load()
493 WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), in kgd_gfx_v9_4_3_set_address_watch()
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A Djpeg_v4_0_3.c118 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_sw_init()
211 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_start_sriov()
327 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_hw_init()
342 VCN, GET_INST(VCN, i), in jpeg_v4_0_3_hw_init()
485 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_start()
572 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_stop()
629 JPEG, GET_INST(JPEG, ring->me), in jpeg_v4_0_3_dec_ring_get_wptr()
921 JPEG, GET_INST(JPEG, i), in jpeg_v4_0_3_is_idle()
943 JPEG, GET_INST(JPEG, i), in jpeg_v4_0_3_wait_for_idle()
1121 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_set_dec_ring_funcs()
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A Dvcn_v4_0_3.c153 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_sw_init()
276 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_hw_init()
287 VCN, GET_INST(VCN, ring->me), in vcn_v4_0_3_hw_init()
295 VCN, GET_INST(VCN, ring->me), in vcn_v4_0_3_hw_init()
385 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_mc_resume()
930 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_start_sriov()
1105 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_start()
1304 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_stop()
1541 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_set_unified_ring_funcs()
1783 inst_id = GET_INST(VCN, i); in vcn_v4_0_3_dump_ip_state()
[all …]
A Damdgpu_vcn.h147 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \
150 VCN, GET_INST(VCN, inst_idx), \
189 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \
192 VCN, GET_INST(VCN, inst_idx), \
A Dgmc_v9_0.c880 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
882 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
893 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
895 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
908 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
910 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
923 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
925 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
A Dsdma_v4_4_2.c112 u32 dev_inst = GET_INST(SDMA0, instance); in sdma_v4_4_2_get_reg_offset()
1850 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); in sdma_v4_4_2_get_clockgating_state()
1855 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); in sdma_v4_4_2_get_clockgating_state()
1997 dev_inst = GET_INST(SDMA0, i); in sdma_v4_4_2_set_ring_funcs()
2229 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); in sdma_v4_4_2_inst_query_ras_error_count()
2267 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); in sdma_v4_4_2_inst_reset_ras_error_count()
A Dsoc15_common.h28 #define GET_INST(ip, inst) \ macro
A Dnbio_v7_9.c83 dev_inst = GET_INST(SDMA0, instance); in nbio_v7_9_sdma_doorbell_range()
A Dgmc_v11_0.c237 1 << vmid, GET_INST(GC, 0)); in gmc_v11_0_flush_gpu_tlb()
A Dgmc_v12_0.c311 1 << vmid, GET_INST(GC, 0)); in gmc_v12_0_flush_gpu_tlb()
A Dgmc_v10_0.c276 1 << vmid, GET_INST(GC, 0)); in gmc_v10_0_flush_gpu_tlb()
A Damdgpu_device.c682 ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, GET_INST(GC, xcc_id)); in amdgpu_device_xcc_rreg()
813 amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, GET_INST(GC, xcc_id)); in amdgpu_device_xcc_wreg()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0_6_ppt.c973 xcc_id = GET_INST(GC, 0); in smu_v13_0_6_get_smu_metrics_data()
2342 xcc_id = GET_INST(GC, i); in smu_v13_0_6_get_gpu_metrics()
2350 inst = GET_INST(VCN, i); in smu_v13_0_6_get_gpu_metrics()
2366 gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak) >> GET_INST(GC, 0); in smu_v13_0_6_get_gpu_metrics()
2419 inst = GET_INST(JPEG, i); in smu_v13_0_6_get_gpu_metrics()
2428 inst = GET_INST(VCN, i); in smu_v13_0_6_get_gpu_metrics()
/linux/drivers/gpu/drm/amd/amdkfd/
A Dkfd_device.c677 mapped_xcc = GET_INST(GC, xcc); in kfd_setup_interrupt_bitmap()

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