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Searched refs:HDP (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dhdp_v4_0.c58 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); in hdp_v4_0_invalidate_hdp()
61 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); in hdp_v4_0_invalidate_hdp()
76 err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); in hdp_v4_0_query_ras_error_count()
85 WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0); in hdp_v4_0_reset_ras_error_count()
88 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); in hdp_v4_0_reset_ras_error_count()
108 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); in hdp_v4_0_update_clock_gating()
124 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); in hdp_v4_0_update_clock_gating()
140 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); in hdp_v4_0_get_clockgating_state()
149 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); in hdp_v4_0_init_registers()
159 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); in hdp_v4_0_init_registers()
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A Dhdp_v5_0.c44 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); in hdp_v5_0_invalidate_hdp()
47 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); in hdp_v5_0_invalidate_hdp()
63 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_update_mem_power_gating()
71 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_0_update_mem_power_gating()
142 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_0_update_mem_power_gating()
153 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_medium_grain_clock_gating()
173 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_0_update_medium_grain_clock_gating()
189 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_get_clockgating_state()
199 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_get_clockgating_state()
212 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); in hdp_v5_0_init_registers()
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A Dhdp_v6_0.c55 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1); in hdp_v6_0_update_clock_gating()
57 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v6_0_update_clock_gating()
58 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v6_0_update_clock_gating()
65 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
67 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
86 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v6_0_update_clock_gating()
122 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v6_0_update_clock_gating()
130 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
132 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
141 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v6_0_get_clockgating_state()
A Dhdp_v5_2.c54 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_mem_power_gating()
55 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v5_2_update_mem_power_gating()
62 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_mem_power_gating()
81 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_2_update_mem_power_gating()
116 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_2_update_mem_power_gating()
125 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_mem_power_gating()
136 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_medium_grain_clock_gating()
156 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_medium_grain_clock_gating()
165 tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_get_clockgating_state()
175 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v5_2_get_clockgating_state()
A Dhdp_v7_0.c51 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL); in hdp_v7_0_update_clock_gating()
52 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v7_0_update_clock_gating()
58 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v7_0_update_clock_gating()
77 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v7_0_update_clock_gating()
113 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v7_0_update_clock_gating()
120 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v7_0_update_clock_gating()
129 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v7_0_get_clockgating_state()
/linux/include/dt-bindings/clock/
A Dstm32mp13-clks.h72 #define HDP 44 macro
A Dstm32mp1-clks.h68 #define HDP 55 macro
/linux/arch/arm64/boot/dts/freescale/
A Dimx8-apalis-v1.1.dtsi463 /* Set signals depending on HDP device type, 0 DP, 1 HDMI */
/linux/drivers/clk/stm32/
A Dclk-stm32mp13.c1362 STM32_GATE_CFG(HDP, hdp, SECF_NONE),
A Dclk-stm32mp1.c1936 PCLK(HDP, "hdp", "pclk3", 0, G_HDP),

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