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Searched refs:HIWORD_UPDATE (Results 1 – 25 of 38) sorted by relevance

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/linux/sound/soc/rockchip/
A Drockchip_i2s_tdm.h360 #define RK3568_I2S3_SCLK_SRC_FROM_TX HIWORD_UPDATE(1, 7, 7)
361 #define RK3568_I2S3_SCLK_SRC_FROM_RX HIWORD_UPDATE(0, 7, 7)
362 #define RK3568_I2S3_LRCK_SRC_FROM_TX HIWORD_UPDATE(1, 6, 6)
379 #define RK3568_I2S3_MCLK_IE HIWORD_UPDATE(0, 3, 3)
380 #define RK3568_I2S3_MCLK_OE HIWORD_UPDATE(1, 3, 3)
381 #define RK3568_I2S2_MCLK_IE HIWORD_UPDATE(0, 2, 2)
382 #define RK3568_I2S2_MCLK_OE HIWORD_UPDATE(1, 2, 2)
383 #define RK3568_I2S1_MCLK_TX_IE HIWORD_UPDATE(0, 1, 1)
384 #define RK3568_I2S1_MCLK_TX_OE HIWORD_UPDATE(1, 1, 1)
385 #define RK3568_I2S1_MCLK_RX_IE HIWORD_UPDATE(0, 0, 0)
[all …]
/linux/drivers/soc/rockchip/
A Dgrf.c14 #define HIWORD_UPDATE(val, mask, shift) \ macro
35 { "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
47 { "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
48 { "vpu main clock", RK3128_GRF_SOC_CON1, HIWORD_UPDATE(0, 1, 10) },
59 { "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
71 { "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
72 { "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
83 { "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) },
94 { "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
105 { "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) },
[all …]
/linux/drivers/gpu/drm/rockchip/
A Drockchip_lvds.h109 #define HIWORD_UPDATE(v, h, l) ((GENMASK(h, l) << 16) | ((v) << (l))) macro
112 #define PX30_LVDS_TIE_CLKS(val) HIWORD_UPDATE(val, 8, 8)
113 #define PX30_LVDS_INVERT_CLKS(val) HIWORD_UPDATE(val, 9, 9)
114 #define PX30_LVDS_INVERT_DCLK(val) HIWORD_UPDATE(val, 5, 5)
117 #define PX30_LVDS_FORMAT(val) HIWORD_UPDATE(val, 14, 13)
118 #define PX30_LVDS_MODE_EN(val) HIWORD_UPDATE(val, 12, 12)
119 #define PX30_LVDS_MSBSEL(val) HIWORD_UPDATE(val, 11, 11)
120 #define PX30_LVDS_P2S_EN(val) HIWORD_UPDATE(val, 6, 6)
121 #define PX30_LVDS_VOP_SEL(val) HIWORD_UPDATE(val, 1, 1)
A Ddw_hdmi-rockchip.c57 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
385 HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL | in dw_hdmi_rk3228_setup_hpd()
392 HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK, in dw_hdmi_rk3228_setup_hpd()
407 HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V, in dw_hdmi_rk3328_read_hpd()
412 HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V | in dw_hdmi_rk3328_read_hpd()
426 HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V | in dw_hdmi_rk3328_setup_hpd()
431 HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF | in dw_hdmi_rk3328_setup_hpd()
436 HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK, in dw_hdmi_rk3328_setup_hpd()
466 .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
503 .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
[all …]
A Ddw-mipi-dsi-rockchip.c210 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
1488 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1542 HIWORD_UPDATE(0, RK3399_TXRX_SRC_SEL_ISP0)); in rk3399_dphy_tx1rx1_init()
1544 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ)); in rk3399_dphy_tx1rx1_init()
1546 HIWORD_UPDATE(0, RK3399_TXRX_BASEDIR)); in rk3399_dphy_tx1rx1_init()
1548 HIWORD_UPDATE(0, RK3399_DSI1_ENABLE)); in rk3399_dphy_tx1rx1_init()
1562 HIWORD_UPDATE(0, RK3399_TXRX_MASTERSLAVEZ)); in rk3399_dphy_tx1rx1_power_on()
1567 HIWORD_UPDATE(0, RK3399_DSI1_FORCERXMODE)); in rk3399_dphy_tx1rx1_power_on()
1573 HIWORD_UPDATE(0, RK3399_TXRX_TURNREQUEST)); in rk3399_dphy_tx1rx1_power_on()
1575 HIWORD_UPDATE(RK3399_DSI1_TURNDISABLE, in rk3399_dphy_tx1rx1_power_on()
[all …]
A Danalogix_dp-rockchip.c40 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
452 .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
453 .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
459 .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
460 .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
/linux/drivers/phy/rockchip/
A Dphy-rockchip-emmc.c23 #define HIWORD_UPDATE(val, mask, shift) \ macro
108 HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF, in rockchip_emmc_phy_power()
113 HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE, in rockchip_emmc_phy_power()
166 HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON, in rockchip_emmc_phy_power()
189 HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK, in rockchip_emmc_phy_power()
195 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE, in rockchip_emmc_phy_power()
290 HIWORD_UPDATE(rk_phy->drive_impedance, in rockchip_emmc_phy_power_on()
297 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA, in rockchip_emmc_phy_power_on()
304 HIWORD_UPDATE(rk_phy->output_tapdelay_select, in rockchip_emmc_phy_power_on()
311 HIWORD_UPDATE(rk_phy->enable_strobe_pulldown, in rockchip_emmc_phy_power_on()
A Dphy-rockchip-pcie.c25 #define HIWORD_UPDATE(val, mask, shift) \ macro
103 HIWORD_UPDATE(data, in phy_wr_cfg()
106 HIWORD_UPDATE(addr, in phy_wr_cfg()
111 HIWORD_UPDATE(PHY_CFG_WR_ENABLE, in phy_wr_cfg()
116 HIWORD_UPDATE(PHY_CFG_WR_DISABLE, in phy_wr_cfg()
131 HIWORD_UPDATE(PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_off()
152 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_off()
179 HIWORD_UPDATE(PHY_CFG_PLL_LOCK, in rockchip_pcie_phy_power_on()
185 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_on()
236 HIWORD_UPDATE(PHY_CFG_PLL_LOCK, in rockchip_pcie_phy_power_on()
A Dphy-rockchip-usb.c27 #define HIWORD_UPDATE(val, mask) \ macro
82 u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ); in rockchip_usb_phy_power()
335 val = HIWORD_UPDATE(UOC_CON0_COMMON_ON_N in rockchip_init_usb_uart_common()
345 val = HIWORD_UPDATE(UOC_CON2_SOFT_CON_SEL, in rockchip_init_usb_uart_common()
351 val = HIWORD_UPDATE(UOC_CON3_UTMI_OPMODE_NODRIVING in rockchip_init_usb_uart_common()
383 val = HIWORD_UPDATE(RK3188_UOC0_CON0_BYPASSSEL in rk3188_init_usb_uart()
433 val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL in rk3288_init_usb_uart()
A Dphy-rockchip-inno-csidphy.c74 #define HIWORD_UPDATE(val, mask, shift) \ macro
150 HIWORD_UPDATE(value, reg->mask, reg->shift)); in write_grf_reg()
/linux/drivers/clk/rockchip/
A Dclk-pll.c272 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), in rockchip_rk3036_pll_enable()
283 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, in rockchip_rk3036_pll_disable()
451 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, in rockchip_rk3066_pll_set_params()
465 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0), in rockchip_rk3066_pll_set_params()
507 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), in rockchip_rk3066_pll_enable()
518 writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN, in rockchip_rk3066_pll_disable()
756 writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0), in rockchip_rk3399_pll_enable()
767 writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN, in rockchip_rk3399_pll_disable()
948 writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, in rockchip_rk3588_pll_set_params()
964 writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0), in rockchip_rk3588_pll_set_params()
[all …]
A Dclk-cpu.c199 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i], in rockchip_cpuclk_pre_rate_change()
209 writel(HIWORD_UPDATE(reg_data->mux_core_alt, in rockchip_cpuclk_pre_rate_change()
214 writel(HIWORD_UPDATE(reg_data->mux_core_alt, in rockchip_cpuclk_pre_rate_change()
251 writel(HIWORD_UPDATE(reg_data->mux_core_main, in rockchip_cpuclk_post_rate_change()
256 writel(HIWORD_UPDATE(reg_data->mux_core_main, in rockchip_cpuclk_post_rate_change()
265 writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i], in rockchip_cpuclk_post_rate_change()
A Dclk-rk3188.c112 .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
118 .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
120 HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
122 HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
124 HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \
164 .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
A Dclk-rk3588.c153 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \
169 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \
185 HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \
192 .val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \
194 HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK, \
201 .val = HIWORD_UPDATE(_aclkm - 1, RK3588_ACLKM_DSU_DIV_MASK, \
203 HIWORD_UPDATE(_aclkmp - 1, RK3588_ACLKMP_DSU_DIV_MASK, \
205 HIWORD_UPDATE(_aclks - 1, RK3588_ACLKS_DSU_DIV_MASK, \
212 .val = HIWORD_UPDATE(_periph - 1, RK3588_PERIPH_DSU_DIV_MASK, \
219 .val = HIWORD_UPDATE(_gicclk - 1, RK3588_GICCLK_DSU_DIV_MASK, \
[all …]
A Dclk-inverter.c49 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), in rockchip_inv_set_phase()
A Dclk-rk3288.c138 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
140 HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
146 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \
148 HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \
150 HIWORD_UPDATE(_pclk_dbg_pre, \
A Dclk-rk3568.c120 .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \
122 HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \
124 HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \
131 .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \
138 .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \
140 HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \
147 .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \
149 HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \
A Dclk-mmc-phase.c137 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), in rockchip_mmc_set_phase()
A Dclk-rk3036.c86 .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \
453 writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10), in rk3036_clk_init()
A Dclk-rk3368.c188 .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \
194 .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \
196 HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \
/linux/drivers/pci/controller/
A Dpcie-rockchip.h22 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) macro
23 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
33 #define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0)
36 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
38 #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0)
39 #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
43 #define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0)
45 #define PCIE_CLIENT_INT_PEND_ST_NORMAL HIWORD_UPDATE(0x0001, 0)
/linux/drivers/net/ethernet/stmicro/stmmac/
A Ddwmac-rk.c84 #define HIWORD_UPDATE(val, mask, shift) \ macro
161 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
162 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
270 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
271 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
416 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
417 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
556 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
557 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1608 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
[all …]
/linux/drivers/pci/controller/dwc/
A Dpcie-dw-rockchip.c30 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) macro
31 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
32 #define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val)
37 #define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0)
39 #define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8)
/linux/drivers/mmc/host/
A Ddw_mmc-rockchip.c27 #define HIWORD_UPDATE(val, mask, shift) \ macro
151 mci_writel(host, TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1)); in rockchip_mmc_set_internal_phase()
153 mci_writel(host, TIMING_CON0, HIWORD_UPDATE(raw_value, 0x07ff, 1)); in rockchip_mmc_set_internal_phase()
/linux/drivers/devfreq/event/
A Drockchip-dfi.c33 #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) macro
145 writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | in rockchip_dfi_enable()
163 writel_relaxed(HIWORD_UPDATE(ctrl, DDRMON_CTRL_DDR_TYPE_MASK), in rockchip_dfi_enable()
167 writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN), in rockchip_dfi_enable()
197 writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN), in rockchip_dfi_disable()

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