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Searched refs:IS_VALLEYVIEW (Results 1 – 25 of 59) sorted by relevance

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/linux/drivers/gpu/drm/i915/
A Dvlv_sideband.c45 if (IS_VALLEYVIEW(i915)) { in __vlv_punit_get()
53 if (IS_VALLEYVIEW(i915)) in __vlv_punit_put()
A Dvlv_suspend.c386 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_suspend_complete()
431 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_resume_prepare()
461 if (!IS_VALLEYVIEW(i915)) in vlv_suspend_init()
A Di915_irq.c1316 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_handler()
1341 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_reset()
1366 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_postinstall()
/linux/drivers/gpu/drm/i915/display/
A Dg4x_dp.c73 } else if (IS_VALLEYVIEW(dev_priv)) { in g4x_dp_set_clock()
480 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_link_down()
696 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_enable_dp()
706 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_enable_dp()
1276 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_encoder_reset()
1352 } else if (IS_VALLEYVIEW(dev_priv)) { in g4x_dp_init()
1375 else if (IS_VALLEYVIEW(dev_priv)) in g4x_dp_init()
1384 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || in g4x_dp_init()
A Dintel_pps.c33 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in pps_name()
357 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_num_pps()
411 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in pps_initial_setup()
503 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pps_get_registers()
550 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_power()
564 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_vdd()
1558 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in pps_init_registers()
1616 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_encoder_reset()
1656 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in pps_init_late()
1716 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_setup()
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A Dintel_pipe_crc.c410 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in get_new_crc_ctl_reg()
540 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_is_valid_crc_source()
616 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_crtc_set_crc_source()
A Dintel_vga.c19 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_vga_cntrl_reg()
A Dintel_sprite_uapi.c63 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_sprite_set_colorkey_ioctl()
A Di9xx_plane.c875 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
909 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_primary_plane_create()
932 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_primary_plane_create()
951 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
A Dintel_dsi_vbt.c425 else if (IS_VALLEYVIEW(i915)) in mipi_exec_gpio()
897 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_vbt_gpio_init()
903 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { in intel_dsi_vbt_gpio_init()
A Dintel_crt.c364 else if (IS_VALLEYVIEW(dev_priv)) in intel_crt_mode_valid()
587 if (IS_VALLEYVIEW(dev_priv)) in intel_crt_detect_hotplug()
1020 else if (IS_VALLEYVIEW(dev_priv)) in intel_crt_init()
A Dintel_hotplug_irq.c139 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in intel_hpd_init_pins()
422 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_ack()
464 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_handler()
479 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_hpd_irq_handler()
A Dintel_cdclk.c533 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) in vlv_calc_cdclk()
545 if (IS_VALLEYVIEW(dev_priv)) { in vlv_calc_voltage_level()
580 if (IS_VALLEYVIEW(dev_priv)) in vlv_get_cdclk()
2812 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_crtc_compute_min_cdclk()
2821 IS_VALLEYVIEW(dev_priv)) in intel_crtc_compute_min_cdclk()
3456 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_update_max_cdclk()
3488 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
3576 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_read_rawclk()
3800 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
A Dintel_lpe_audio.c187 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in lpe_audio_detect()
A Dg4x_hdmi.c674 if (IS_G4X(i915) || IS_VALLEYVIEW(i915)) in is_hdmi_port_valid()
746 } else if (IS_VALLEYVIEW(dev_priv)) { in g4x_hdmi_init()
A Dintel_drrs.c83 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_drrs_set_refresh_rate_pipeconf()
A Dintel_wm.c199 IS_VALLEYVIEW(dev_priv) || in wm_latency_show()
/linux/drivers/gpu/drm/i915/selftests/
A Dintel_uncore.c174 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) { in live_forcewake_ops()
285 !IS_VALLEYVIEW(gt->i915) && in live_forcewake_domains()
/linux/drivers/gpu/drm/i915/gt/
A Dintel_rc6.c618 else if (IS_VALLEYVIEW(i915)) in intel_rc6_init()
656 else if (IS_VALLEYVIEW(i915)) in intel_rc6_enable()
814 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_rc6_residency_ns()
A Dselftest_rc6.c51 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
A Dintel_rps.c706 if (IS_VALLEYVIEW(gt->i915)) in rps_set_power()
843 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in rps_set()
1547 else if (IS_VALLEYVIEW(i915)) in intel_rps_enable()
1647 else if (IS_VALLEYVIEW(i915)) in intel_gpu_freq()
1664 else if (IS_VALLEYVIEW(i915)) in intel_freq_opcode()
1995 else if (IS_VALLEYVIEW(i915)) in intel_rps_init()
2082 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_rps_get_cagf()
2111 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in __read_cagf()
A Dintel_gt_pm_debugfs.c327 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in drpc_show()
358 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_gt_pm_frequency_dump()
A Dintel_ggtt_fencing.c578 if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) { in detect_bit_6_swizzle()
853 !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) in intel_ggtt_init_fences()
/linux/drivers/gpu/drm/xe/compat-i915-headers/
A Di915_drv.h46 #define IS_VALLEYVIEW(dev_priv) (dev_priv && 0) macro
/linux/drivers/gpu/drm/i915/soc/
A Dintel_gmch.c89 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_gmch_bar_setup()

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