| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| A D | link_dp_training.h | 83 union lane_status ln_status[LANE_COUNT_DP_MAX],
85 union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
112 const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
113 struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
159 const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
160 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]);
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| A D | link_dp_training_fixed_vs_pe_retimer.c | 46 union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX]) in dp_fixed_vs_pe_read_lane_adjust() argument
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
74 const union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX], in dp_fixed_vs_pe_set_retimer_lane_settings() argument
168 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in perform_fixed_vs_pe_nontransparent_training_sequence()
326 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; in dp_perform_fixed_vs_pe_training_sequence()
328 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dp_perform_fixed_vs_pe_training_sequence()
457 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in dp_perform_fixed_vs_pe_training_sequence()
458 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dp_perform_fixed_vs_pe_training_sequence()
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| A D | link_dp_training_fixed_vs_pe_retimer.h | 38 const union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX],
43 union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX]);
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| A D | link_dp_training_8b_10b.c | 165 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; in perform_8b_10b_clock_recovery_sequence()
167 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in perform_8b_10b_clock_recovery_sequence()
286 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in perform_8b_10b_channel_equalization_sequence()
287 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in perform_8b_10b_channel_equalization_sequence()
402 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_perform_8b_10b_link_training()
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| A D | link_dp_training_128b_132b.c | 80 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in dp_perform_128b_132b_channel_eq_done_sequence()
81 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dp_perform_128b_132b_channel_eq_done_sequence()
165 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in dp_perform_128b_132b_cds_done_sequence()
166 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dp_perform_128b_132b_cds_done_sequence()
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| A D | link_dp_training.c | 303 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in maximize_lane_settings() argument
347 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in maximize_lane_settings()
361 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_hw_to_dpcd_lane_settings()
597 union lane_status ln_status[LANE_COUNT_DP_MAX], in dp_get_lane_status_and_lane_adjust() argument
599 union lane_adjust ln_adjust[LANE_COUNT_DP_MAX], in dp_get_lane_status_and_lane_adjust() argument
681 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in override_lane_settings() argument
692 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in override_lane_settings()
748 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in override_training_settings()
850 const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX], in dp_decide_lane_settings() argument
856 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_decide_lane_settings()
[all …]
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| A D | link_dp_training_dpia.c | 296 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in dpia_training_cr_non_transparent()
298 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dpia_training_cr_non_transparent()
462 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in dpia_training_cr_transparent()
464 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dpia_training_cr_transparent()
592 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in dpia_training_eq_non_transparent()
593 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dpia_training_eq_non_transparent()
736 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; in dpia_training_eq_transparent()
737 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0}; in dpia_training_eq_transparent()
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| /linux/drivers/gpu/drm/amd/display/include/ |
| A D | link_service_types.h | 112 struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX];
113 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX];
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| /linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| A D | link_hwss_dio.h | 54 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
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| A D | link_hwss_dpia.c | 76 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in set_dio_dpia_lane_settings() argument
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| A D | link_hwss_hpo_dp.c | 161 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in set_hpo_dp_lane_settings() argument
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| A D | link_hwss_hpo_fixed_vs_pe_retimer_dp.c | 179 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in set_hpo_fixed_vs_pe_retimer_dp_lane_settings() argument
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| A D | link_hwss_dio.c | 185 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in set_dio_dp_lane_settings() argument
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | link_hwss.h | 65 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
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| /linux/drivers/gpu/drm/amd/display/dc/virtual/ |
| A D | virtual_link_encoder.c | 65 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) {} in virtual_link_encoder_dp_set_lane_settings() argument
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | link_encoder.h | 133 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_link_encoder.h | 283 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
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| A D | dce_link_encoder.c | 1323 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in dce110_link_encoder_dp_set_lane_settings() argument
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| /linux/drivers/gpu/drm/amd/display/dc/link/accessories/ |
| A D | link_dp_cts.c | 598 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0}; in dp_set_test_pattern()
766 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) in dp_set_test_pattern()
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| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| A D | dcn10_link_encoder.h | 618 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
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| A D | dcn10_link_encoder.c | 1101 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) in dcn10_link_encoder_dp_set_lane_settings() argument
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dc_dp_types.h | 38 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR enumerator
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| A D | dc.h | 1681 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| A D | link_dpms.c | 1184 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; in poll_for_allocation_change_trigger()
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