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Searched refs:MAX_PIPES (Results 1 – 25 of 70) sorted by relevance

123

/linux/drivers/gpu/drm/amd/display/dc/inc/
A Dcore_types.h229 struct mem_input *mis[MAX_PIPES];
230 struct hubp *hubps[MAX_PIPES];
233 struct dpp *dpps[MAX_PIPES];
240 struct dce_aux *engines[MAX_PIPES];
241 struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
242 struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
274 struct dc_3dlut *mpc_lut[MAX_PIPES];
307 struct abm *multiple_abms[MAX_PIPES];
490 struct pipe_ctx pipe_ctx[MAX_PIPES];
492 bool is_audio_acquired[MAX_PIPES];
[all …]
A Dresource.h380 struct pipe_ctx *opp_heads[MAX_PIPES]);
390 struct pipe_ctx *dpp_pipes[MAX_PIPES]);
399 struct pipe_ctx *dpp_pipes[MAX_PIPES]);
/linux/drivers/gpu/drm/amd/display/dc/core/
A Ddc_link_enc_cfg.c113 for (i = 0; i < MAX_PIPES; i++) { in remove_link_enc_assignment()
249 for (i = 0; i < MAX_PIPES; i++) { in get_link_enc_used_by_link()
265 for (i = 0; i < MAX_PIPES; i++) { in clear_enc_assignments()
315 for (i = 0; i < MAX_PIPES; i++) in link_enc_cfg_link_encs_assign()
411 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
417 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
430 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
481 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_stream_using_link_enc()
520 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_link_enc_used_by_link()
544 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_next_avail_link_enc()
[all …]
A Ddc_stream.c237 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_attributes()
347 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_position()
635 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_vblank_counter()
665 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_send_dp_sdp()
698 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_scanoutpos()
725 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_dmdata_status_done()
731 if (i == MAX_PIPES) in dc_stream_dmdata_status_done()
755 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_set_dynamic_metadata()
761 if (i == MAX_PIPES) in dc_stream_set_dynamic_metadata()
797 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_pipe_ctx()
A Ddc.c403 for (i = 0; i < MAX_PIPES; i++) { in set_long_vtotal()
461 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_adjust_vmin_vmax()
498 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_last_used_drr_vtotal()
530 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_crtc_position()
591 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_forward_crc_window()
598 if (i == MAX_PIPES) in dc_stream_forward_crc_window()
712 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_crc()
718 if (i == MAX_PIPES) in dc_stream_get_crc()
4238 char force_odm[MAX_PIPES];
5877 if (i == MAX_PIPES) { in dc_notify_vsync_int_state()
[all …]
A Ddc_resource.c684 for (i = 0; i < MAX_PIPES; i++) { in resource_find_used_clk_src_for_sharing()
1435 struct pipe_ctx *opp_heads[MAX_PIPES]; in resource_build_test_pattern_params()
1646 for (i = 0; i < MAX_PIPES; i++) { in resource_build_scaling_params_for_context()
1900 for (i = 0; i < MAX_PIPES; i++) { in resource_get_otg_master_for_stream()
1926 ASSERT(i < MAX_PIPES); in resource_get_opp_heads_for_otg_master()
1945 ASSERT(i < MAX_PIPES); in resource_get_dpp_pipes_for_opp_head()
1959 for (j = 0; j < MAX_PIPES; j++) { in resource_get_dpp_pipes_for_plane()
1968 if (j < MAX_PIPES) { in resource_get_dpp_pipes_for_plane()
2166 for (i = 0; i < MAX_PIPES; i++) { in resource_is_pipe_topology_changed()
2296 struct pipe_ctx *opp_heads[MAX_PIPES]; in resource_log_pipe_for_stream()
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A Ddc_debug.c314 int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0}; in context_timing_trace()
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
A Ddcn20_dccg.h132 type OTG_ADD_PIXEL[MAX_PIPES];\
133 type OTG_DROP_PIXEL[MAX_PIPES];
168 type DTBCLK_DTO_ENABLE[MAX_PIPES];\
169 type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
170 type PIPE_DTO_SRC_SEL[MAX_PIPES];\
171 type DTBCLK_DTO_DIV[MAX_PIPES];\
360 type DP_DTO_ENABLE[MAX_PIPES];
394 uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
395 uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
427 uint32_t DP_DTO_MODULO[MAX_PIPES];
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_internal_types.h131 struct dml2_pipe_combine_factor odm_factors[MAX_PIPES];
132 struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES][MAX_PIPES];
A Ddml2_dc_resource_mgmt.c47 unsigned int odm_slice_end_x[MAX_PIPES];
48 struct pipe_ctx *next_higher_pipe_for_odm_slice[MAX_PIPES];
328 unsigned int preferred_pipe_candidates[MAX_PIPES] = {0}; in find_more_pipes_for_stream()
329 unsigned int last_resort_pipe_candidates[MAX_PIPES] = {0}; in find_more_pipes_for_stream()
394 unsigned int preferred_pipe_candidates[MAX_PIPES] = {0}; in find_more_free_pipes()
613 unsigned int pipes[MAX_PIPES] = {0}; in assign_pipes_to_stream()
651 unsigned int pipes[MAX_PIPES] = {0}; in assign_pipes_to_plane()
918 struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0}; in get_source_mpc_factor()
934 struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES]) in populate_mpc_factors_for_stream() argument
950 struct dml2_pipe_combine_factor odm_factors[MAX_PIPES]) in populate_odm_factors() argument
[all …]
A Ddml2_wrapper.h99 struct pipe_ctx *opp_heads[MAX_PIPES]);
102 struct pipe_ctx *dpp_pipes[MAX_PIPES]);
233 enum dml2_force_pstate_methods force_pstate_method_values[MAX_PIPES];
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dhw_shared.h45 #define MAX_PIPES 6 macro
46 #define MAX_PHANTOM_PIPES (MAX_PIPES / 2)
47 #define MAX_LINKS (MAX_PIPES * 2 +2)
A Dopp.h231 int dpp[MAX_PIPES];
232 int mpcc[MAX_PIPES];
240 bool mpcc_disconnect_pending[MAX_PIPES];
A Ddccg.h77 int pipe_dppclk_khz[MAX_PIPES];
79 bool dpp_clock_gated[MAX_PIPES];
A Dpg_cntl.h35 bool pg_pipe_res_enable[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/
A Ddcn35_pg_cntl.c145 if (dsc_inst < MAX_PIPES) in pg_cntl35_dsc_pg_control()
241 if (hubp_dpp_inst < MAX_PIPES) { in pg_cntl35_hubp_dpp_pg_control()
362 if (mpcc_inst < MAX_PIPES) in pg_cntl35_mpcc_pg_control()
372 if (opp_inst < MAX_PIPES) in pg_cntl35_opp_pg_control()
382 if (optc_inst < MAX_PIPES) in pg_cntl35_optc_pg_control()
539 memset(base->pg_pipe_res_enable, 0, PG_HW_PIPE_RESOURCES_NUM_ELEMENT * MAX_PIPES * sizeof(bool)); in pg_cntl35_create()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/
A Ddcn401_optc.c59 bool first_preferred_memory_for_opp[MAX_PIPES] = {0}; in decide_odm_mem_bit_map()
60 bool second_preferred_memory_for_opp[MAX_PIPES] = {0}; in decide_odm_mem_bit_map()
83 for (i = 0; i < MAX_PIPES; i++) { in decide_odm_mem_bit_map()
94 for (i = 0; i < MAX_PIPES; i++) { in decide_odm_mem_bit_map()
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clock_source.h228 uint32_t PHASE[MAX_PIPES];
229 uint32_t MODULO[MAX_PIPES];
230 uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_hwseq.c162 int opp_inst[MAX_PIPES] = {0}; in dcn314_update_odm()
362 bool otg_disabled[MAX_PIPES] = {false}; in dcn314_resync_fifo_dccg_dio()
390 int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst }; in dcn314_resync_fifo_dccg_dio()
443 for (i = 0; i < MAX_PIPES; i++) { in apply_symclk_on_tx_off_wa()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.c514 struct pipe_ctx *pipe_ctx_list[MAX_PIPES]; in dcn32_auto_dpm_test_log()
517 for (int i = 0; i < MAX_PIPES; i++) { in dcn32_auto_dpm_test_log()
564 uint32_t pix_clk_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
565 int p_state_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
566 int disp_src_width_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
567 int disp_src_height_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
568 uint64_t disp_src_refresh_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
569 bool is_scaled_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
/linux/drivers/gpu/drm/amd/display/dc/link/
A Dlink_dpms.h42 struct pipe_ctx *pipes[MAX_PIPES]);
A Dlink_resource.c40 for (i = 0; i < MAX_PIPES; i++) { in link_get_cur_link_res()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_mst_types.c920 bool bpp_increased[MAX_PIPES]; in increase_dsc_bpp()
921 int initial_slack[MAX_PIPES]; in increase_dsc_bpp()
1023 bool tried[MAX_PIPES]; in try_disable_dsc()
1024 int kbps_increase[MAX_PIPES]; in try_disable_dsc()
1116 struct dsc_mst_fairness_params params[MAX_PIPES]; in compute_mst_dsc_configs_for_link()
1268 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES]; in is_dsc_need_re_compute()
1284 for (i = 0; i < MAX_PIPES; i++) in is_dsc_need_re_compute()
1399 bool computed_streams[MAX_PIPES]; in compute_mst_dsc_configs_for_state()
1469 bool computed_streams[MAX_PIPES]; in pre_compute_mst_dsc_configs_for_state()
A Damdgpu_dm_debugfs.c1270 for (i = 0; i < MAX_PIPES; i++) { in odm_combine_segments_show()
1548 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_clock_en_read()
1651 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_clock_en_write()
1738 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_width_read()
1839 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_width_write()
1926 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_height_read()
2027 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_height_write()
2110 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_bits_per_pixel_read()
2208 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_bits_per_pixel_write()
2289 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_pic_width_read()
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/linux/drivers/gpu/drm/amd/display/dc/link/accessories/
A Dlink_dp_cts.c68 struct pipe_ctx *pipes[MAX_PIPES]; in dp_retrain_link_dp_test()
604 for (i = 0; i < MAX_PIPES; i++) { in dp_set_test_pattern()
911 for (i = 0; i < MAX_PIPES; i++) { in dp_set_preferred_link_settings()
922 if (i == MAX_PIPES) in dp_set_preferred_link_settings()

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