| /linux/Documentation/devicetree/bindings/sound/ |
| A D | mt8173-rt5650.txt | 16 - mediatek,mclk: the MCLK source
17 0 : external oscillator, MCLK = 12.288M
18 1 : internal source from mt8173, MCLK = sampling rate*256
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| A D | cs42l56.txt | 20 Frequency = MCLK / 4 * (N+2)
22 MCLK = Where MCLK is the frequency of the mclk signal after the MCLKDIV2 circuit.
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| A D | tas2552.txt | 18 tas2552 can receive its reference clock via MCLK, BCLK, IVCLKIN pin or use the
20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
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| A D | cirrus,cs42l51.yaml | 30 - const: MCLK
70 clock-names = "MCLK";
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| A D | nuvoton,nau8325.yaml | 46 When clock detection is enabled, it will detect whether MCLK
47 and FS are within the range. MCLK range is from 2.048MHz to 24.576MHz.
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| A D | max9860.txt | 14 - clocks : A clock specifier for the clock connected as MCLK.
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| A D | everest,es8316.yaml | 28 - description: clock for master clock (MCLK)
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| A D | st,stm32-sai.yaml | 86 - description: MCLK clock from a SAI set as master clock provider.
92 - const: MCLK
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| A D | fsl,saif.yaml | 40 description: Configure the I2S device as MCLK clock provider.
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| /linux/Documentation/devicetree/bindings/media/ |
| A D | pxa-camera.txt | 12 sensor master clock MCLK
13 - clock-frequency: host interface is driving MCLK, and MCLK rate is this rate
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| /linux/drivers/spi/ |
| A D | spi-mpc52xx-psc.c | 26 #define MCLK 20000000 /* PSC port MClk in hz */ macro
93 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
95 ccr |= (MCLK / 1000000 - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
250 mclken_div = 512000000 / MCLK; in mpc52xx_psc_spi_port_config()
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| /linux/sound/soc/meson/ |
| A D | aiu-encoder-spdif.c | 144 ret = clk_set_rate(aiu->spdif.clks[MCLK].clk, mrate); in aiu_encoder_spdif_hw_params()
183 ret = clk_set_parent(aiu->spdif.clks[MCLK].clk, in aiu_encoder_spdif_startup()
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| A D | aiu-encoder-i2s.c | 153 fs = DIV_ROUND_CLOSEST(clk_get_rate(aiu->i2s.clks[MCLK].clk), srate); in aiu_encoder_i2s_set_clocks()
279 ret = clk_set_rate(aiu->i2s.clks[MCLK].clk, freq); in aiu_encoder_i2s_set_sysclk()
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| A D | aiu.h | 20 MCLK, enumerator
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| A D | aiu.c | 202 [MCLK] = "i2s_mclk",
209 [MCLK] = "spdif_mclk_sel"
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| /linux/Documentation/sound/soc/ |
| A D | clocking.rst | 12 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
34 - BCLK = MCLK / x, or
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| /linux/drivers/media/pci/ddbridge/ |
| A D | ddbridge-sx8.c | 14 static const u32 MCLK = (1550000000 / 12); variable
187 if (p->symbol_rate >= (MCLK / 2)) in start()
209 if (p->symbol_rate >= MCLK / 2) { in start()
244 i = (p->symbol_rate > (MCLK / 2)) ? 3 : 7; in start()
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| /linux/Documentation/devicetree/bindings/display/bridge/ |
| A D | sil,sii9022.yaml | 74 description: MCLK input. MCLK can be used to produce HDMI audio CTS values.
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| /linux/arch/arm/boot/dts/st/ |
| A D | stm32mp157c-phycore-stm32mp15-som.dtsi | 94 "Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */
95 "Capture", "MCLK";
458 clock-names = "sai_ck", "MCLK";
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| A D | stm32mp15xx-dkx.dtsi | 78 "Playback" , "MCLK",
79 "Capture" , "MCLK",
221 clock-names = "MCLK";
528 clock-names = "sai_ck", "MCLK";
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| /linux/arch/arm64/boot/dts/qcom/ |
| A D | sdm845-oneplus-enchilada.dts | 60 audio-routing = "RX_BIAS", "MCLK",
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| A D | sdm845-oneplus-fajita.dts | 42 audio-routing = "RX_BIAS", "MCLK",
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | fsl,sai-clock.yaml | 18 clock of the second SAI as a MCLK clock for an audio codec, for example.
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| A D | qcom,gcc-msm8916.yaml | 35 - description: External MCLK clock
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| A D | starfive,jh7110-voutcrg.yaml | 24 - description: Vout Top HDMI MCLK
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