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Searched refs:MDIO_MMD_AN (Results 1 – 25 of 40) sorted by relevance

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/linux/drivers/net/phy/
A Dphy-c45.c326 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_an_disable_aneg()
346 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_restart_aneg()
370 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_check_and_restart_aneg()
404 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_aneg_done()
425 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_read_link()
529 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_read_lpa()
548 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); in genphy_c45_read_lpa()
698 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in genphy_c45_write_eee_adv()
716 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in genphy_c45_write_eee_adv()
732 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in genphy_c45_write_eee_adv()
[all …]
A Dbcm84881.c113 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in bcm84881_config_aneg()
129 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in bcm84881_aneg_done()
133 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR); in bcm84881_aneg_done()
146 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in bcm84881_read_status()
155 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in bcm84881_read_status()
159 bmsr = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_C22 + MII_BMSR); in bcm84881_read_status()
185 val = phy_read_mmd(phydev, MDIO_MMD_AN, in bcm84881_read_status()
A Dmarvell-88q2xxx.c106 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
124 { MDIO_MMD_AN, 0x8032, 0x2020 },
125 { MDIO_MMD_AN, 0x8031, 0xa28 },
126 { MDIO_MMD_AN, 0x8031, 0xc28 },
136 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
143 { MDIO_MMD_AN, MDIO_AN_T1_CTRL, 0x0 },
166 { MDIO_MMD_AN, 0x8032, 0x2020 },
167 { MDIO_MMD_AN, 0x8031, 0xa28 },
168 { MDIO_MMD_AN, 0x8031, 0xc28 },
203 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_MMD_AN_MV_STAT); in mv88q2xxx_read_link_gbit()
[all …]
A Dadin1100.c84 ret = phy_read_mmd(phydev, MDIO_MMD_AN, ADIN_AN_PHY_INST_STATUS); in adin_read_status()
117 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN); in adin_config_aneg()
120 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN); in adin_config_aneg()
126 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, in adin_config_aneg()
135 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, in adin_config_aneg()
A Dteranetics.c62 reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in teranetics_read_status()
A Dbcm-phy-lib.c377 val = phy_read_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL); in bcm_phy_set_eee()
386 phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val); in bcm_phy_set_eee()
389 val = phy_read_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV); in bcm_phy_set_eee()
405 phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val); in bcm_phy_set_eee()
512 { "phy_lpi_count", MDIO_MMD_AN, BRCM_CL45VEN_EEE_LPI_CNT, 0, 16 },
A Dmarvell10g.c632 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
638 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN, in mv2110_set_mactype()
646 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
957 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000, in mv3310_config_aneg()
1044 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in mv3310_read_status_copper()
1101 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000); in mv3310_read_status_copper()
A Drealtek.c717 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { in rtlgen_read_mmd()
721 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) { in rtlgen_read_mmd()
737 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) { in rtlgen_write_mmd()
759 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { in rtl822x_read_mmd()
763 } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) { in rtl822x_read_mmd()
780 if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) { in rtl822x_write_mmd()
/linux/drivers/net/ethernet/amd/xgbe/
A Dxgbe-mdio.c184 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0); in xgbe_an73_clear_interrupts()
189 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); in xgbe_an73_disable_interrupts()
407 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); in xgbe_an73_set()
416 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); in xgbe_an73_set()
532 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); in xgbe_an73_tx_xnp()
533 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); in xgbe_an73_tx_xnp()
534 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg); in xgbe_an73_tx_xnp()
555 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); in xgbe_an73_rx_bpa()
569 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP); in xgbe_an73_rx_xnp()
1570 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1)); in xgbe_dump_phy_registers()
[all …]
A Dxgbe-phy-v1.c243 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); in xgbe_phy_an_outcome()
244 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); in xgbe_phy_an_outcome()
267 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); in xgbe_phy_an_outcome()
268 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); in xgbe_phy_an_outcome()
291 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_phy_an_outcome()
292 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_phy_an_outcome()
A Dxgbe-phy-v2.c1707 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); in xgbe_phy_an73_redrv_outcome()
1708 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); in xgbe_phy_an73_redrv_outcome()
1770 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_phy_an73_redrv_outcome()
1771 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_phy_an73_redrv_outcome()
1788 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); in xgbe_phy_an73_outcome()
1789 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); in xgbe_phy_an73_outcome()
1812 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); in xgbe_phy_an73_outcome()
1813 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); in xgbe_phy_an73_outcome()
1828 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_phy_an73_outcome()
1829 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_phy_an73_outcome()
/linux/drivers/vfio/platform/reset/
A Dvfio_platform_amdxgbe.c85 value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1); in vfio_platform_amdxgbe_reset()
87 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1, value); in vfio_platform_amdxgbe_reset()
90 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_AN_INTMASK, 0); in vfio_platform_amdxgbe_reset()
93 xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_AN_INT, 0); in vfio_platform_amdxgbe_reset()
/linux/drivers/net/ethernet/chelsio/cxgb3/
A Daq100x.c134 MDIO_MMD_AN, MDIO_CTRL1, in aq100x_autoneg_enable()
147 MDIO_MMD_AN, MDIO_CTRL1, in aq100x_autoneg_restart()
162 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in aq100x_advertise()
173 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, AQ_1G_CTRL, in aq100x_advertise()
188 err = t3_mdio_change_bits(phy, MDIO_MMD_AN, MDIO_AN_ADVERTISE, in aq100x_advertise()
223 err = t3_mdio_read(phy, MDIO_MMD_AN, AQ_ANEG_STAT, &v); in aq100x_get_link_status()
/linux/drivers/net/phy/qcom/
A Dqca808x.c107 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, in qca808x_phy_fast_retrain_config()
163 ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE); in qca808x_is_1g_only()
204 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, in qca808x_config_init()
257 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in qca808x_read_status()
400 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in qca808x_config_aneg()
492 return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_hw_control_set()
523 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in qca808x_led_hw_control_get()
553 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_hw_control_reset()
619 return phy_modify_mmd(phydev, MDIO_MMD_AN, in qca808x_led_polarity_set()
A Dqca807x.c232 return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, mask, in qca807x_led_hw_control_set()
264 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in qca807x_led_hw_control_get()
283 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in qca807x_led_hw_control_get()
325 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, mask); in qca807x_led_hw_control_reset()
374 val = phy_read_mmd(priv->phy, MDIO_MMD_AN, reg); in qca807x_gpio_get()
387 val = phy_read_mmd(priv->phy, MDIO_MMD_AN, reg); in qca807x_gpio_set()
392 phy_write_mmd(priv->phy, MDIO_MMD_AN, reg, val); in qca807x_gpio_set()
667 MDIO_MMD_AN, in qca807x_sfp_insert()
772 control_dac = phy_read_mmd(phydev, MDIO_MMD_AN, in qca807x_config_init()
781 return phy_write_mmd(phydev, MDIO_MMD_AN, in qca807x_config_init()
A Dqcom-phy-lib.c626 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_reg_hw_control_enable()
635 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in qca808x_led_reg_hw_control_status()
643 return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_reg_brightness_set()
657 ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL, in qca808x_led_reg_blink_set()
664 ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg, in qca808x_led_reg_blink_set()
/linux/drivers/net/ethernet/sfc/falcon/
A Dmdio_10g.c55 if (mmd != MDIO_MMD_AN) { in ef4_mdio_check_mmd()
285 ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); in ef4_mdio_an_reconfigure()
291 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1); in ef4_mdio_an_reconfigure()
293 ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg); in ef4_mdio_an_reconfigure()
307 ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_LPA)); in ef4_mdio_get_pause()
A Dtenxpress.c263 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1); in sfx7101_check_bad_lp()
446 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); in tenxpress_get_link_ksettings()
449 reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in tenxpress_get_link_ksettings()
473 ef4_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in sfx7101_set_npage_adv()
/linux/drivers/net/phy/aquantia/
A Daquantia_main.c187 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, in aqr_config_aneg()
207 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); in aqr_config_intr()
212 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, in aqr_config_intr()
242 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, in aqr_handle_interrupt()
262 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); in aqr_read_status()
282 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); in aqr107_read_rate()
387 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); in aqr107_get_downshift()
411 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, in aqr107_set_downshift()
552 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); in aqr107_link_change_notify()
560 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); in aqr107_link_change_notify()
[all …]
/linux/drivers/net/
A Dmdio.c142 mdio_set_flag(mdio, mdio->prtad, MDIO_MMD_AN, MDIO_CTRL1, in mdio45_nway_restart()
153 reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, addr); in mdio45_get_an()
259 reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, in mdio45_ethtool_gset_npage()
277 MDIO_MMD_AN, MDIO_STAT1); in mdio45_ethtool_gset_npage()
430 reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, in mdio45_ethtool_ksettings_get_npage()
448 MDIO_MMD_AN, MDIO_STAT1); in mdio45_ethtool_ksettings_get_npage()
574 devad = MDIO_MMD_AN; in mdio_mii_ioctl()
/linux/drivers/net/ethernet/intel/ixgbe/
A Dixgbe_phy.c1118 MDIO_MMD_AN, &autoneg_reg); in ixgbe_setup_phy_link_generic()
1142 MDIO_MMD_AN, autoneg_reg); in ixgbe_setup_phy_link_generic()
1160 MDIO_MMD_AN, &autoneg_reg); in ixgbe_setup_phy_link_generic()
1165 MDIO_MMD_AN, autoneg_reg); in ixgbe_setup_phy_link_generic()
1340 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
1348 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
1355 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
1363 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
1370 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
1379 MDIO_MMD_AN, in ixgbe_setup_phy_link_tnx()
[all …]
A Dixgbe_x550.c2388 MDIO_MMD_AN, &reg); in ixgbe_get_lasi_ext_t_x550em()
2395 MDIO_MMD_AN, &reg); in ixgbe_get_lasi_ext_t_x550em()
2438 MDIO_MMD_AN, &reg); in ixgbe_enable_lasi_ext_t_x550em()
2446 MDIO_MMD_AN, reg); in ixgbe_enable_lasi_ext_t_x550em()
2613 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, in ixgbe_ext_phy_t_x550em_get_link()
2665 MDIO_MMD_AN, in ixgbe_setup_internal_phy_t_x550em()
2829 MDIO_MMD_AN, in ixgbe_get_lcd_t_x550em()
3065 MDIO_MMD_AN, in ixgbe_enter_lplu_t_x550em()
3087 MDIO_MMD_AN, in ixgbe_enter_lplu_t_x550em()
3093 MDIO_MMD_AN, in ixgbe_enter_lplu_t_x550em()
[all …]
/linux/drivers/net/pcs/
A Dpcs-xpcs.c418 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV3, adv); in _xpcs_config_aneg_c73()
431 ret = xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV2, adv); in _xpcs_config_aneg_c73()
442 return xpcs_write(xpcs, MDIO_MMD_AN, DW_SR_AN_ADV1, adv); in _xpcs_config_aneg_c73()
454 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_CTRL1); in xpcs_config_aneg_c73()
460 return xpcs_write(xpcs, MDIO_MMD_AN, MDIO_CTRL1, ret); in xpcs_config_aneg_c73()
470 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA); in xpcs_aneg_done_c73()
501 ret = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_AN_LPA + i); in xpcs_read_lpa_c73()
942 an_stat1 = xpcs_read(xpcs, MDIO_MMD_AN, MDIO_STAT1); in xpcs_get_state_c73()
/linux/include/uapi/linux/
A Dmdio.h25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */ macro
157 #define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)
/linux/rust/kernel/net/phy/
A Dreg.rs155 pub const AN: Self = Mmd(uapi::MDIO_MMD_AN as u8);

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