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Searched refs:MLXSW_ITEM32 (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/net/ethernet/mellanox/mlxsw/
A Dcmd.h241 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1);
252 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8);
272 MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8);
277 MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8);
665 MLXSW_ITEM32(cmd_mbox, config_profile,
803 MLXSW_ITEM32(cmd_mbox, config_profile,
809 MLXSW_ITEM32(cmd_mbox, config_profile,
1021 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8);
1180 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, c_eqn, 0x00, 24, 1);
1187 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, st, 0x00, 8, 1);
[all …]
A Dpci_hw.h74 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
86 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
91 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
143 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
191 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
192 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
198 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
199 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
206 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
213 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
[all …]
A Dreg.h91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
132 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
170 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
204 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
604 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
890 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
1594 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
2490 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
2498 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
2606 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
[all …]
A Dcore_acl_flex_actions.c26 MLXSW_ITEM32(afa, set, type, 0xA0, 28, 4);
38 MLXSW_ITEM32(afa, set, goto_g, 0xA4, 29, 1);
61 MLXSW_ITEM32(afa, all, action_type, 0x00, 24, 6);
1108 MLXSW_ITEM32(afa, vlan, vid, 0x04, 0, 12);
1122 MLXSW_ITEM32(afa, vlan, pcp, 0x08, 8, 3);
1478 MLXSW_ITEM32(afa, qos, ecn, 0x04, 24, 2);
1499 MLXSW_ITEM32(afa, qos, dscp, 0x04, 0, 6);
1723 MLXSW_ITEM32(afa, polcnt, c_p, 0x00, 31, 1);
1748 MLXSW_ITEM32(afa, polcnt, pid, 0x08, 0, 14);
2022 MLXSW_ITEM32(afa, ip, s_d, 0x00, 31, 1);
[all …]
A Dcore.c309 MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4);
315 MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5);
321 MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11);
329 MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1);
346 MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7);
356 MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1);
365 MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7);
370 MLXSW_ITEM32(emad, op_tlv, class, 0x04, 0, 8);
416 MLXSW_ITEM32(emad, reg_tlv, type, 0x00, 27, 5);
421 MLXSW_ITEM32(emad, reg_tlv, len, 0x00, 16, 11);
[all …]
A Dspectrum.c114 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
121 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
126 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
131 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
137 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
142 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
148 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
153 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
163 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
170 MLXSW_ITEM32(tx, hdr, fid, 0x08, 16, 16);
[all …]
A Ditem.h356 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ macro

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