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Searched refs:MMC_TIMING_MMC_DDR52 (Results 1 – 25 of 40) sorted by relevance

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/linux/drivers/mmc/host/
A Ddw_mmc-hi3798cv200.c32 if (ios->timing == MMC_TIMING_MMC_DDR52 || in dw_mci_hi3798cv200_set_ios()
40 if (ios->timing == MMC_TIMING_MMC_DDR52) in dw_mci_hi3798cv200_set_ios()
A Dsdhci-of-arasan.c750 case MMC_TIMING_MMC_DDR52: in sdhci_zynqmp_sdcardclk_set_phase()
819 case MMC_TIMING_MMC_DDR52: in sdhci_zynqmp_sampleclk_set_phase()
879 case MMC_TIMING_MMC_DDR52: in sdhci_versal_sdcardclk_set_phase()
946 case MMC_TIMING_MMC_DDR52: in sdhci_versal_sampleclk_set_phase()
1000 case MMC_TIMING_MMC_DDR52: in sdhci_versal_net_emmc_sdcardclk_set_phase()
1046 case MMC_TIMING_MMC_DDR52: in sdhci_versal_net_emmc_sampleclk_set_phase()
1321 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52, in arasan_dt_parse_clk_phases()
A Ddw_mmc-starfive.c31 if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) { in dw_mci_starfive_set_ios()
A Ddw_mmc-rockchip.c194 ios->timing == MMC_TIMING_MMC_DDR52) in dw_mci_rk3288_set_ios()
252 case MMC_TIMING_MMC_DDR52: in dw_mci_rk3288_set_ios()
A Ddw_mmc-hi3798mv200.c43 if (ios->timing == MMC_TIMING_MMC_DDR52 in dw_mci_hi3798mv200_set_ios()
A Dsdhci-xenon.c217 (timing == MMC_TIMING_MMC_DDR52)) in xenon_set_uhs_signaling()
362 host->timing == MMC_TIMING_MMC_DDR52) in xenon_execute_tuning()
A Dsdhci-xenon-phy.c651 case MMC_TIMING_MMC_DDR52: in xenon_emmc_phy_set()
783 case MMC_TIMING_MMC_DDR52: in xenon_hs_delay_adj()
A Dsdhci-pci-arasan.c283 case MMC_TIMING_MMC_DDR52: in arasan_select_phy_clock()
A Dsdhci-omap.c830 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) in sdhci_omap_set_uhs_signaling()
1173 pinctrl_state[MMC_TIMING_MMC_DDR52] = state; in sdhci_omap_config_iodelay_pinctrl_state()
1179 pinctrl_state[MMC_TIMING_MMC_DDR52] = state; in sdhci_omap_config_iodelay_pinctrl_state()
A Dsdhci-sprd.c110 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
361 case MMC_TIMING_MMC_DDR52: in sdhci_sprd_set_uhs_signaling()
A Dsunxi-mmc.c742 ios->timing != MMC_TIMING_MMC_DDR52) { in sunxi_mmc_clk_set_phase()
787 if (ios->timing == MMC_TIMING_MMC_DDR52 && in sunxi_mmc_clk_set_rate()
892 ios->timing == MMC_TIMING_MMC_DDR52) in sunxi_mmc_set_clk()
A Dsdhci-st.c292 case MMC_TIMING_MMC_DDR52: in sdhci_st_set_uhs_signaling()
A Dsdhci-of-at91.c105 if (timing == MMC_TIMING_MMC_DDR52) { in sdhci_at91_set_uhs_signaling()
A Dsdhci_am654.c132 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
713 if (i <= MMC_TIMING_MMC_DDR52) in sdhci_am654_get_otap_delay()
A Dsdhci-brcmstb.c181 (timing == MMC_TIMING_MMC_DDR52)) in sdhci_brcmstb_set_uhs_signaling()
A Dsdhci-pxav3.c265 case MMC_TIMING_MMC_DDR52: in pxav3_set_uhs_signaling()
A Dsdhci-cadence.c304 case MMC_TIMING_MMC_DDR52: in sdhci_cdns_set_uhs_signaling()
A Dmeson-gx-mmc.c568 case MMC_TIMING_MMC_DDR52: in meson_mmc_prepare_ios_clock()
588 case MMC_TIMING_MMC_DDR52: in meson_mmc_check_resampling()
A Ddw_mmc-exynos.c323 case MMC_TIMING_MMC_DDR52: in dw_mci_exynos_set_ios()
A Dmmci_stm32_sdmmc.c302 if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 || in mmci_sdmmc_set_clkreg()
A Drtsx_pci_sdmmc.c1036 case MMC_TIMING_MMC_DDR52: in sd_set_timing()
1117 case MMC_TIMING_MMC_DDR52: in sdmmc_set_ios()
/linux/drivers/mmc/core/
A Dhost.h73 return card->host->ios.timing == MMC_TIMING_MMC_DDR52; in mmc_card_ddr52()
A Ddebugfs.c147 case MMC_TIMING_MMC_DDR52: in mmc_ios_show()
A Dhost.c255 &map->phase[MMC_TIMING_MMC_DDR52]); in mmc_of_parse_clk_phase()
/linux/include/linux/mmc/
A Dhost.h62 #define MMC_TIMING_MMC_DDR52 8 macro

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