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Searched refs:MMC_TIMING_UHS_DDR50 (Results 1 – 25 of 37) sorted by relevance

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/linux/drivers/mmc/host/
A Ddw_mmc-starfive.c31 if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) { in dw_mci_starfive_set_ios()
A Dsdhci-of-arasan.c749 case MMC_TIMING_UHS_DDR50: in sdhci_zynqmp_sdcardclk_set_phase()
818 case MMC_TIMING_UHS_DDR50: in sdhci_zynqmp_sampleclk_set_phase()
878 case MMC_TIMING_UHS_DDR50: in sdhci_versal_sdcardclk_set_phase()
945 case MMC_TIMING_UHS_DDR50: in sdhci_versal_sampleclk_set_phase()
1112 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_execute_tuning()
1319 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50, in arasan_dt_parse_clk_phases()
A Ddw_mmc-hi3798cv200.c33 ios->timing == MMC_TIMING_UHS_DDR50) in dw_mci_hi3798cv200_set_ios()
A Dsdhci-pxav3.c266 case MMC_TIMING_UHS_DDR50: in pxav3_set_uhs_signaling()
279 uhs == MMC_TIMING_UHS_DDR50) { in pxav3_set_uhs_signaling()
A Ddw_mmc-hi3798mv200.c44 || ios->timing == MMC_TIMING_UHS_DDR50) in dw_mci_hi3798mv200_set_ios()
A Dsdhci-xenon.c216 else if ((timing == MMC_TIMING_UHS_DDR50) || in xenon_set_uhs_signaling()
361 if (host->timing == MMC_TIMING_UHS_DDR50 || in xenon_execute_tuning()
A Dsdhci-xenon-phy.c650 case MMC_TIMING_UHS_DDR50: in xenon_emmc_phy_set()
784 case MMC_TIMING_UHS_DDR50: in xenon_hs_delay_adj()
A Drtsx_pci_sdmmc.c1037 case MMC_TIMING_UHS_DDR50: in sd_set_timing()
1118 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()
1338 case MMC_TIMING_UHS_DDR50: in sdmmc_execute_tuning()
1353 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in sdmmc_execute_tuning()
A Dsdhci-pci-arasan.c284 case MMC_TIMING_UHS_DDR50: in arasan_select_phy_clock()
A Dsdhci-st.c291 case MMC_TIMING_UHS_DDR50: in sdhci_st_set_uhs_signaling()
A Dsdhci-esdhc-imx.c1107 if (host->timing == MMC_TIMING_UHS_DDR50) in usdhc_execute_tuning()
1245 case MMC_TIMING_UHS_DDR50: in esdhc_change_pinstate()
1332 case MMC_TIMING_UHS_DDR50: in esdhc_set_uhs_signaling()
A Dsdhci-brcmstb.c180 else if ((timing == MMC_TIMING_UHS_DDR50) || in sdhci_brcmstb_set_uhs_signaling()
A Dusdhi6rol0.c750 if (ios->timing != MMC_TIMING_UHS_DDR50) { in usdhi6_clk_set()
853 if (ios->timing == MMC_TIMING_UHS_DDR50) in usdhi6_set_ios()
860 mode = ios->timing == MMC_TIMING_UHS_DDR50; in usdhi6_set_ios()
A Dsdhci-omap.c830 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) in sdhci_omap_set_uhs_signaling()
1153 pinctrl_state[MMC_TIMING_UHS_DDR50] = state; in sdhci_omap_config_iodelay_pinctrl_state()
A Ddw_mmc-exynos.c334 case MMC_TIMING_UHS_DDR50: in dw_mci_exynos_set_ios()
A Dowl-mmc.c524 if (ios->timing == MMC_TIMING_UHS_DDR50) { in owl_mmc_set_ios()
A Drtsx_usb_sdmmc.c1060 case MMC_TIMING_UHS_DDR50: in sd_set_timing()
1124 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()
A Dsunxi-mmc.c741 if (ios->timing != MMC_TIMING_UHS_DDR50 && in sunxi_mmc_clk_set_phase()
891 if (ios->timing == MMC_TIMING_UHS_DDR50 || in sunxi_mmc_set_clk()
A Dmmci_stm32_sdmmc.c303 host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) in mmci_sdmmc_set_clkreg()
A Dsdhci.c1870 case MMC_TIMING_UHS_DDR50: in sdhci_get_preset_value()
2278 else if ((timing == MMC_TIMING_UHS_DDR50) || in sdhci_set_uhs_signaling()
2294 case MMC_TIMING_UHS_DDR50: in sdhci_timing_has_preset()
2401 ios->timing == MMC_TIMING_UHS_DDR50 || in sdhci_set_ios()
2903 case MMC_TIMING_UHS_DDR50: in sdhci_execute_tuning()
A Dsdhci-sprd.c360 case MMC_TIMING_UHS_DDR50: in sdhci_sprd_set_uhs_signaling()
/linux/include/linux/mmc/
A Dhost.h61 #define MMC_TIMING_UHS_DDR50 7 macro
615 card->host->ios.timing <= MMC_TIMING_UHS_DDR50; in mmc_card_uhs()
/linux/drivers/mmc/core/
A Ddebugfs.c144 case MMC_TIMING_UHS_DDR50: in mmc_ios_show()
A Dsd.c486 timing = MMC_TIMING_UHS_DDR50; in sd_set_bus_speed_mode()
659 card->host->ios.timing == MMC_TIMING_UHS_DDR50 || in mmc_sd_init_uhs_card()
670 if (err && card->host->ios.timing == MMC_TIMING_UHS_DDR50) { in mmc_sd_init_uhs_card()
A Dhost.c253 &map->phase[MMC_TIMING_UHS_DDR50]); in mmc_of_parse_clk_phase()

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