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Searched refs:MUX (Results 1 – 25 of 124) sorted by relevance

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/linux/drivers/clk/samsung/
A Dclk-exynosautov920.c565 MUX(MOUT_CLKCMU_ACC_NOC, "mout_clkcmu_acc_noc",
567 MUX(MOUT_CLKCMU_ACC_ORB, "mout_clkcmu_acc_orb",
571 MUX(MOUT_CLKCMU_APM_NOC, "mout_clkcmu_apm_noc",
575 MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu",
577 MUX(MOUT_CLKCMU_AUD_NOC, "mout_clkcmu_aud_noc",
608 MUX(MOUT_CLKCMU_DNC_NOC, "mout_clkcmu_dnc_noc",
634 MUX(MOUT_CLKCMU_DSP_NOC, "mout_clkcmu_dsp_noc",
677 MUX(MOUT_CLKCMU_ISP_NOC, "mout_clkcmu_isp_noc",
681 MUX(MOUT_CLKCMU_M2M_NOC, "mout_clkcmu_m2m_noc",
687 MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc",
[all …]
A Dclk-exynos5420.c494 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
508 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
520 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
552 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
562 MUX(0, "mout_aclk333_432_isp", mout_group4_p,
575 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
608 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
611 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
713 MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
723 MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
[all …]
A Dclk-exynos4.c427 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
428 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
449 MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
453 MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
461 MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
485 MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
486 MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
487 MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
513 MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
532 MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp",
[all …]
A Dclk-s5pv210.c379 MUX(MOUT_EPLL, "mout_epll", mout_epll_p, CLK_SRC0, 8, 1),
380 MUX(MOUT_MPLL, "mout_mpll", mout_mpll_p, CLK_SRC0, 4, 1),
381 MUX(MOUT_APLL, "mout_apll", mout_apll_p, CLK_SRC0, 0, 1),
388 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1),
395 MUX(MOUT_DAC, "mout_dac", mout_dac_p, CLK_SRC1, 8, 1),
397 MUX(MOUT_HDMI, "mout_hdmi", mout_hdmi_p, CLK_SRC1, 0, 1),
399 MUX(MOUT_G2D, "mout_g2d", mout_group1_p, CLK_SRC2, 8, 2),
400 MUX(MOUT_MFC, "mout_mfc", mout_group1_p, CLK_SRC2, 4, 2),
401 MUX(MOUT_G3D, "mout_g3d", mout_group1_p, CLK_SRC2, 0, 2),
416 MUX(MOUT_PWM, "mout_pwm", mout_group2_p, CLK_SRC5, 12, 4),
[all …]
A Dclk-exynos7.c93 MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
95 MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
106 MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
476 MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
479 MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
482 MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
484 MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
839 MUX(0, "mout_aclk_peris_66_user",
1046 MUX(0, "mout_phyclk_ufs20_rx1_symbol_user",
1048 MUX(0, "mout_phyclk_ufs20_rx0_symbol_user",
[all …]
A Dclk-exynos5260.c226 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER,
230 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER,
234 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER,
243 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER,
259 MUX(DISP_MOUT_HDMI_PHY_PIXEL,
263 MUX(DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER,
267 MUX(DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER,
447 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER,
451 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER,
459 MUX(FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER,
[all …]
A Dclk-exynos5250.c261 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
283 MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
284 MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
285 MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
301 MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
313 MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
314 MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
315 MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
318 MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
320 MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
[all …]
A Dclk-exynos5410.c90 MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
91 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
93 MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
94 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
96 MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
99 MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
102 MUX(0, "sclk_epll", epll_p, SRC_TOP2, 12, 1),
104 MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
108 MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
109 MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
[all …]
A Dclk-exynosautov9.c455 MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost",
475 MUX(MOUT_CLKCMU_BUSC_BUS, "mout_clkcmu_busc_bus",
483 MUX(MOUT_CLKCMU_CORE_BUS, "mout_clkcmu_core_bus",
503 MUX(MOUT_CLKCMU_DPTX_BUS, "mout_clkcmu_dptx_bus",
509 MUX(MOUT_CLKCMU_DPUM_BUS, "mout_clkcmu_dpum_bus",
547 MUX(MOUT_CLKCMU_G2D_MSCL, "mout_clkcmu_g2d_mscl",
564 MUX(MOUT_CLKCMU_ISPB_BUS, "mout_clkcmu_ispb_bus",
568 MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc",
570 MUX(MOUT_CLKCMU_MFC_WFD, "mout_clkcmu_mfc_wfd",
576 MUX(MOUT_CLKCMU_MIF_BUSP, "mout_clkcmu_mif_busp",
[all …]
A Dclk-exynos3250.c254 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
259 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
262 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
269 MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
274 MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
278 MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
283 MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
287 MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
292 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
307 MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
[all …]
A Dclk-exynos5433.c2158 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2162 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2166 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2170 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2174 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2711 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2714 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2717 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
4762 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
4766 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
[all …]
A Dclk-exynos7885.c203 MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
205 MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
207 MUX(CLK_MOUT_CORE_G3D, "mout_core_g3d", mout_core_g3d_p,
211 MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
231 MUX(CLK_MOUT_FSYS_BUS, "mout_fsys_bus", mout_fsys_bus_p,
477 MUX(CLK_MOUT_PERI_UART0_USER, "mout_peri_uart0_user",
479 MUX(CLK_MOUT_PERI_UART1_USER, "mout_peri_uart1_user",
481 MUX(CLK_MOUT_PERI_UART2_USER, "mout_peri_uart2_user",
483 MUX(CLK_MOUT_PERI_USI0_USER, "mout_peri_usi0_user",
485 MUX(CLK_MOUT_PERI_USI1_USER, "mout_peri_usi1_user",
[all …]
A Dclk-exynos850.c317 MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
321 MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
325 MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p,
351 MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
359 MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p,
367 MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p,
369 MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p,
371 MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p,
373 MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p,
391 MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p,
[all …]
A Dclk-gs101.c2159 MUX(CLK_MOUT_PLL_USB,
2162 MUX(CLK_MOUT_HSI0_ALT_USER,
2165 MUX(CLK_MOUT_HSI0_BUS_USER,
2168 MUX(CLK_MOUT_HSI0_DPGTC_USER,
2171 MUX(CLK_MOUT_HSI0_TCXO_USER,
2174 MUX(CLK_MOUT_HSI0_USB20_USER,
2177 MUX(CLK_MOUT_HSI0_USB31DRD_USER,
2183 MUX(CLK_MOUT_HSI0_BUS,
2186 MUX(CLK_MOUT_HSI0_USB20_REF,
2189 MUX(CLK_MOUT_HSI0_USB31DRD,
[all …]
A Dclk-s3c64xx.c126 MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1),
127 MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1),
128 MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1),
129 MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1),
132 MUX(MOUT_UART, "mout_uart", uart_p, CLK_SRC, 13, 1),
133 MUX(MOUT_SPI0, "mout_spi0", spi_mmc_p, CLK_SRC, 14, 2),
134 MUX(MOUT_SPI1, "mout_spi1", spi_mmc_p, CLK_SRC, 16, 2),
135 MUX(MOUT_MMC0, "mout_mmc0", spi_mmc_p, CLK_SRC, 18, 2),
136 MUX(MOUT_MMC1, "mout_mmc1", spi_mmc_p, CLK_SRC, 20, 2),
137 MUX(MOUT_MMC2, "mout_mmc2", spi_mmc_p, CLK_SRC, 22, 2),
[all …]
A Dclk-fsd.c196 MUX(0, "mout_cmu_cpucl_switchmux", mout_cmu_cpucl_switchmux_p,
501 MUX(0, "mout_peric_eqos_busclk", mout_peric_eqos_busclk_p,
505 MUX(0, "mout_peric_spi_clk", mout_peric_spi_clk_p, PLL_CON0_SPI_CLK, 4, 1),
803 MUX(0, "mout_fsys0_clkcmu_fsys0_unipro", mout_fsys0_clkcmu_fsys0_unipro_p,
807 MUX(0, "mout_fsys0_eqos_rgmii_125_mux1", mout_fsys0_eqos_rgmii_125_mux1_p,
1052 MUX(0, "mout_fsys1_aclk_fsys1_busp_mux", mout_fsys1_aclk_fsys1_busp_mux_p,
1275 MUX(0, "mout_imem_clk_imem_tcuclk", mout_imem_clk_imem_tcuclk_p,
1278 MUX(0, "mout_imem_clk_imem_intmemclk", mout_imem_clk_imem_intmemclk_p,
1489 MUX(0, "mout_mfc_pll", mout_mfc_pll_p, PLL_CON0_PLL_MFC, 4, 1),
1490 MUX(0, "mout_mfc_busp", mout_mfc_busp_p, MUX_MFC_BUSP, 0, 1),
[all …]
/linux/drivers/clk/mediatek/
A Dclk-mt8167.c524 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
534 MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
540 MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
542 MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
572 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
584 MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
586 MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
592 MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
610 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
612 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
[all …]
A Dclk-mt8516.c365 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
369 MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
371 MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
373 MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
393 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
395 MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
397 MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
403 MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
421 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
423 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
[all …]
A Dclk-mt6797.c325 MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
327 MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
331 MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
340 MUX(CLK_TOP_MUX_ULPOSC_SPI_CK_MUX, "ulposc_spi_ck_mux",
344 MUX(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel",
356 MUX(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents,
358 MUX(CLK_TOP_MUX_SCP, "scp_sel", scp_parents,
360 MUX(CLK_TOP_MUX_ATB, "atb_sel", atb_parents,
368 MUX(CLK_TOP_MUX_SSUSB_TOP_SYS, "ssusb_top_sys_sel",
370 MUX(CLK_TOP_MUX_SPM, "spm_sel", spm_parents,
[all …]
/linux/drivers/clk/tegra/
A Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ macro
665 MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor),
669 MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab),
670 MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd),
671 MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile),
672 MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, tegra_clk_dsialp),
673 MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, tegra_clk_dsiblp),
675 MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, tegra_clk_actmon),
685 MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve),
686 MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo),
[all …]
/linux/drivers/clk/pistachio/
A Dclk-pistachio.c124 MUX(CLK_AUDIO_REF_MUX, "audio_refclk_mux", mux_xtal_audio_refclk,
126 MUX(CLK_MIPS_PLL_MUX, "mips_pll_mux", mux_xtal_mips, 0x200, 1),
127 MUX(CLK_AUDIO_PLL_MUX, "audio_pll_mux", mux_xtal_audio, 0x200, 2),
128 MUX(CLK_AUDIO_MUX, "audio_mux", mux_audio_debug, 0x200, 4),
129 MUX(CLK_RPU_V_PLL_MUX, "rpu_v_pll_mux", mux_xtal_rpu_v, 0x200, 5),
131 MUX(CLK_RPU_L_MUX, "rpu_l_mux", mux_rpu_l_mips, 0x200, 7),
132 MUX(CLK_WIFI_PLL_MUX, "wifi_pll_mux", mux_xtal_wifi, 0x200, 8),
136 MUX(CLK_SYS_PLL_MUX, "sys_pll_mux", mux_xtal_sys, 0x200, 13),
137 MUX(CLK_ENET_MUX, "enet_mux", mux_sys_enet, 0x200, 14),
139 MUX(CLK_SD_HOST_MUX, "sd_host_mux", mux_sys_bt, 0x200, 16),
[all …]
/linux/Documentation/i2c/
A Di2c-sysfs.rst10 I2C topology can be complex because of the existence of I2C MUX
32 2. General knowledge of I2C, I2C MUX and I2C topology.
123 `-- 7-0071 (4-channel I2C MUX at 0x71)
128 | `-- 73-0072 (8-channel I2C MUX at 0x72)
165 abstracts an I2C MUX channel under the parent bus.
189 8-channel MUX at address 0x72 behind the channel 1 of the 0x71 MUX. Let us
191 of the 0x72 MUX.
202 There, we see the 0x71 MUX as ``7-0071``. Go inside it::
280 If not specified in DTS, when an I2C MUX driver is applied and the MUX device is
285 MUX channel 0, and all the way to ``i2c-19`` for the MUX channel 3.
[all …]
/linux/drivers/clk/rockchip/
A Dclk-rk3568.c389 MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT,
393 MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT,
397 MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT,
401 MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT,
405 MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT,
409 MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT,
413 MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT,
417 MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT,
421 MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT,
564 MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT,
[all …]
A Dclk-rk3308.c199 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
203 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
207 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
211 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
215 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
219 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
227 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
263 MUX(0, "clk_i2s0_2ch_mux", mux_i2s0_2ch_p, CLK_SET_RATE_PARENT,
284 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
533 MUX(SCLK_MAC, "clk_mac", mux_mac_p, CLK_SET_RATE_PARENT,
[all …]
A Dclk-rk3188.c252 MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0,
330 MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
335 MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,
408 MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0,
547 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
551 MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, CLK_SET_RATE_PARENT,
555 MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, CLK_SET_RATE_PARENT,
593 MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0,
614 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
672 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
[all …]

Completed in 97 milliseconds

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