| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| A D | dcn30_smu11_driver_if.h | 25 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) member
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| A D | smu10_driver_if.h | 51 uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */ member
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| A D | smu9_driver_if.h | 330 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| A D | dcn316_clk_mgr.c | 357 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges()
373 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges()
386 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn316_build_watermark_ranges()
392 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn316_build_watermark_ranges()
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| A D | dcn316_smu.h | 41 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| A D | smu13_driver_if_v13_0_5.h | 52 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| A D | smu13_driver_if_yellow_carp.h | 50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| A D | smu12_driver_if.h | 51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| A D | smu11_driver_if_vangogh.h | 50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| A D | smu13_driver_if_v13_0_4.h | 51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| A D | smu14_driver_if_v14_0_0.h | 46 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| A D | dcn315_smu.h | 42 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| A D | dcn315_clk_mgr.c | 395 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges()
411 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges()
424 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn315_build_watermark_ranges()
430 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn315_build_watermark_ranges()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| A D | vg_clk_mgr.c | 400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
416 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
429 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in vg_build_watermark_ranges()
435 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in vg_build_watermark_ranges()
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| A D | dcn301_smu.h | 56 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| A D | dcn31_clk_mgr.c | 435 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
451 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
464 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn31_build_watermark_ranges()
470 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn31_build_watermark_ranges()
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| A D | dcn31_smu.h | 52 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| A D | dcn35_smu.h | 49 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| A D | dcn35_clk_mgr.c | 656 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn35_build_watermark_ranges()
672 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn35_build_watermark_ranges()
685 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn35_build_watermark_ranges()
691 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn35_build_watermark_ranges()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| A D | dcn314_clk_mgr.c | 500 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges()
516 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges()
529 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn314_build_watermark_ranges()
535 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn314_build_watermark_ranges()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | smu_helper.h | 36 uint16_t MinClock; member
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| A D | smu_helper.c | 728 table->WatermarkRow[1][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
749 table->WatermarkRow[0][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| A D | smu_v13_0_5_ppt.c | 422 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
436 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
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| A D | smu_v13_0_4_ppt.c | 678 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
692 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/ |
| A D | smu9_driver_if.h | 574 uint16_t MinClock; member
|