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Searched refs:NUM_BANKS (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v6_0.c446 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
454 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
462 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
552 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
560 NUM_BANKS(ADDR_SURF_8_BANK); in gfx_v6_0_tiling_mode_table_init()
568 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
576 NUM_BANKS(ADDR_SURF_4_BANK); in gfx_v6_0_tiling_mode_table_init()
584 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
592 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
600 NUM_BANKS(ADDR_SURF_2_BANK); in gfx_v6_0_tiling_mode_table_init()
[all …]
A Dgfx_v8_0.c2194 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2198 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2202 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2206 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2210 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2214 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2218 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2386 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2390 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2394 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
[all …]
A Dgfx_v7_0.c1142 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v7_0_tiling_mode_table_init()
1146 NUM_BANKS(ADDR_SURF_4_BANK)); in gfx_v7_0_tiling_mode_table_init()
1170 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v7_0_tiling_mode_table_init()
1174 NUM_BANKS(ADDR_SURF_4_BANK)); in gfx_v7_0_tiling_mode_table_init()
1321 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v7_0_tiling_mode_table_init()
1325 NUM_BANKS(ADDR_SURF_4_BANK)); in gfx_v7_0_tiling_mode_table_init()
1329 NUM_BANKS(ADDR_SURF_4_BANK)); in gfx_v7_0_tiling_mode_table_init()
1345 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v7_0_tiling_mode_table_init()
1353 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v7_0_tiling_mode_table_init()
1357 NUM_BANKS(ADDR_SURF_4_BANK)); in gfx_v7_0_tiling_mode_table_init()
[all …]
A Dcikd.h197 # define NUM_BANKS(x) ((x) << 6) macro
A Dsdma_v4_4_2.c163 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); in sdma_v4_4_2_inst_init_golden_registers()
169 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, in sdma_v4_4_2_inst_init_golden_registers()
A Dsid.h1218 # define NUM_BANKS(x) ((x) << 20) macro
A Ddce_v6_0.c1963 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v6_0_crtc_do_set_base()
A Ddce_v8_0.c1932 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v8_0_crtc_do_set_base()
A Ddce_v10_0.c1993 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
A Ddce_v11_0.c2043 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
A Dgfx_v9_4_3.c959 NUM_BANKS); in gfx_v9_4_3_gpu_early_init()
A Dgfx_v9_0.c2116 NUM_BANKS); in gfx_v9_0_gpu_early_init()
/linux/drivers/gpu/drm/radeon/
A Dsi.c2500 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2509 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2518 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2527 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2536 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2545 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2554 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2563 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2572 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2698 NUM_BANKS(ADDR_SURF_8_BANK) | in si_tiling_mode_table_init()
[all …]
A Dcik.c2598 NUM_BANKS(ADDR_SURF_8_BANK)); in cik_tiling_mode_table_init()
2602 NUM_BANKS(ADDR_SURF_4_BANK)); in cik_tiling_mode_table_init()
2606 NUM_BANKS(ADDR_SURF_2_BANK)); in cik_tiling_mode_table_init()
2626 NUM_BANKS(ADDR_SURF_8_BANK)); in cik_tiling_mode_table_init()
2630 NUM_BANKS(ADDR_SURF_4_BANK)); in cik_tiling_mode_table_init()
2634 NUM_BANKS(ADDR_SURF_2_BANK)); in cik_tiling_mode_table_init()
2827 NUM_BANKS(ADDR_SURF_8_BANK)); in cik_tiling_mode_table_init()
2831 NUM_BANKS(ADDR_SURF_4_BANK)); in cik_tiling_mode_table_init()
2855 NUM_BANKS(ADDR_SURF_8_BANK)); in cik_tiling_mode_table_init()
2859 NUM_BANKS(ADDR_SURF_4_BANK)); in cik_tiling_mode_table_init()
[all …]
A Dsid.h1221 # define NUM_BANKS(x) ((x) << 20) macro
A Dcikd.h1275 # define NUM_BANKS(x) ((x) << 6) macro
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
A Ddcn10_hubp.h269 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
467 type NUM_BANKS;\
A Ddcn10_hubp.c150 NUM_BANKS, log_2(info->gfx9.num_banks), in hubp1_program_tiling()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_plane.c190 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
/linux/drivers/gpu/drm/amd/include/
A Dnavi10_enum.h1549 typedef enum NUM_BANKS { enum
1555 } NUM_BANKS; typedef

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