Searched refs:OPP_SF (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_opp.h | 95 #define OPP_SF(reg_name, field_name, post_fix)\ macro
122 OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
123 OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\
131 OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\
132 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\
133 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh)
139 OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
145 OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
190 OPP_SF(FMT0_FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
229 OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\
[all …]
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| A D | dce_transform.h | 256 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\
257 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\
258 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh)
272 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\
273 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\
274 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh)
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| /linux/drivers/gpu/drm/amd/display/dc/opp/dcn10/ |
| A D | dcn10_opp.h | 33 #define OPP_SF(reg_name, field_name, post_fix)\ macro
69 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \
81 OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \
82 OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh), \
84 OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh), \
85 OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \
86 OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \
88 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \
89 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \
93 OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/opp/dcn20/ |
| A D | dcn20_opp.h | 33 #define OPP_SF(reg_name, field_name, post_fix)\ macro
65 OPP_SF(DPG0_DPG_CONTROL, DPG_EN, mask_sh), \
66 OPP_SF(DPG0_DPG_CONTROL, DPG_MODE, mask_sh), \
67 OPP_SF(DPG0_DPG_CONTROL, DPG_DYNAMIC_RANGE, mask_sh), \
68 OPP_SF(DPG0_DPG_CONTROL, DPG_BIT_DEPTH, mask_sh), \
69 OPP_SF(DPG0_DPG_CONTROL, DPG_VRES, mask_sh), \
70 OPP_SF(DPG0_DPG_CONTROL, DPG_HRES, mask_sh), \
79 OPP_SF(DPG0_DPG_COLOUR_G_Y, DPG_COLOUR0_G_Y, mask_sh), \
80 OPP_SF(DPG0_DPG_COLOUR_G_Y, DPG_COLOUR1_G_Y, mask_sh), \
82 OPP_SF(DPG0_DPG_RAMP_CONTROL, DPG_INC0, mask_sh), \
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/opp/dcn35/ |
| A D | dcn35_opp.h | 38 OPP_SF(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, mask_sh)
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_opp.h | 33 #define OPP_SF(reg_name, field_name, post_fix)\ macro
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