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Searched refs:OTG_VERT_SYNC_CONTROL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/
A Ddcn10_optc.c734 REG_GET(OTG_VERT_SYNC_CONTROL, in optc1_did_triggered_reset_occur()
749 REG_SET(OTG_VERT_SYNC_CONTROL, 0, in optc1_disable_reset_trigger()
819 REG_SET(OTG_VERT_SYNC_CONTROL, 0, in optc1_enable_crtc_reset()
A Ddcn10_optc.h79 SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
104 uint32_t OTG_VERT_SYNC_CONTROL; member
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/
A Ddcn31_optc.h77 SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
A Ddcn35_resource.h265 SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst),\
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/
A Ddcn314_optc.h78 SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn30/
A Ddcn30_optc.h82 SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.h517 SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.h1035 SRI_ARR(CONTROL, VTG, inst), SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \

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