| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_mode_vba_util_32.h | 313 double OutputBpp,
323 double OutputBpp,
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| A D | display_mode_vba_util_32.c | 1687 double OutputBpp, in dml32_RequiredDTBCLK() argument
1701 return dml_max(PixelClock / 4.0 * OutputBpp / 24.0, 25.0); in dml32_RequiredDTBCLK()
1704 HCActive = dml_ceil(DSCSlices * dml_ceil(OutputBpp * in dml32_RequiredDTBCLK()
1716 double OutputBpp, in dml32_DSCDelayRequirement() argument
1728 if (DSCEnabled == true && OutputBpp != 0) { in dml32_DSCDelayRequirement()
1730 DSCDelayRequirement_val = 4 * (dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, in dml32_DSCDelayRequirement()
1734 DSCDelayRequirement_val = 2 * (dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, in dml32_DSCDelayRequirement()
1738 DSCDelayRequirement_val = dml32_dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, in dml32_DSCDelayRequirement()
1754 dml_print("DML::%s: OutputBpp = %f\n", __func__, OutputBpp); in dml32_DSCDelayRequirement()
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| A D | display_mode_vba_32.c | 3750 mode_lib->vba.OutputBpp[k] = mode_lib->vba.OutputBppPerState[mode_lib->vba.VoltageLevel][k]; in dml32_ModeSupportAndSystemConfigurationFull()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_shared_types.h | 279 double OutputBpp[DML2_MAX_PLANES]; member
472 double OutputBpp[DML2_MAX_PLANES]; member
872 double OutputBpp[DML2_MAX_PLANES]; member
968 double OutputBpp[DML2_MAX_PLANES]; member
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| A D | dml2_core_shared.c | 431 double OutputBpp,
441 double OutputBpp,
1257 s->OutputBpp[k], in dml2_core_shared_mode_support()
1271 &mode_lib->ms.OutputBpp[k], in dml2_core_shared_mode_support()
1484 mode_lib->ms.OutputBpp[k], in dml2_core_shared_mode_support()
1572 mode_lib->ms.OutputBpp[k], in dml2_core_shared_mode_support()
2825 mode_lib->ms.support.OutputBpp[k] = mode_lib->ms.OutputBpp[k]; in dml2_core_shared_mode_support()
6923 double OutputBpp, in RequiredDTBCLK() argument
6946 double OutputBpp, in DSCDelayRequirement() argument
10133 s->OutputBpp[k], in dml2_core_shared_mode_programming()
[all …]
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| A D | dml2_core_dcn4_calcs.c | 4423 double OutputBpp, in RequiredDTBCLK() argument
4446 double OutputBpp, in DSCDelayRequirement() argument
7540 s->OutputBpp[k], in dml_core_mode_support()
7554 &mode_lib->ms.OutputBpp[k], in dml_core_mode_support()
7559 if (s->OutputBpp[k] == 0.0) { in dml_core_mode_support()
7560 s->OutputBpp[k] = mode_lib->ms.OutputBpp[k]; in dml_core_mode_support()
7814 mode_lib->ms.OutputBpp[k], in dml_core_mode_support()
7914 s->OutputBpp[k], in dml_core_mode_support()
9193 mode_lib->ms.support.OutputBpp[k] = mode_lib->ms.OutputBpp[k]; in dml_core_mode_support()
10263 s->OutputBpp[k], in dml_core_mode_programming()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| A D | dml_top_types.h | 358 double OutputBpp[DML2_MAX_PLANES]; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_translation_helper.c | 798 out->OutputBpp[location] = (dml_float_t)output_bpc * 3; in populate_dml_output_cfg_from_stream_state()
802 out->OutputBpp[location] = (output_bpc * 3.0) / 2; in populate_dml_output_cfg_from_stream_state()
809 out->OutputBpp[location] = (dml_float_t)output_bpc * 2; in populate_dml_output_cfg_from_stream_state()
813 out->OutputBpp[location] = (dml_float_t)output_bpc * 3; in populate_dml_output_cfg_from_stream_state()
818 out->OutputBpp[location] = in->timing.dsc_cfg.bits_per_pixel / 16.0; in populate_dml_output_cfg_from_stream_state()
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| A D | dml2_utils.c | 123 dml_output_array->OutputBpp[dst_index] = dml_output_array->OutputBpp[src_index]; in dml2_util_copy_dml_output()
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| A D | display_mode_core_structs.h | 569 …dml_float_t OutputBpp[__DML_NUM_PLANES__]; //< brief Use by mode_programming to specify a output b… member
741 dml_float_t OutputBpp[__DML_NUM_PLANES__]; member
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| A D | display_mode_core.c | 445 dml_float_t OutputBpp,
737 dml_float_t OutputBpp,
4577 dml_float_t OutputBpp, in RequiredDTBCLK() argument
4585 return dml_max(PixelClock / 4.0 * OutputBpp / 24.0, 25.0); in RequiredDTBCLK()
4588 …dml_float_t HCActive = dml_ceil(DSCSlices * dml_ceil(OutputBpp * dml_ceil(HActive / DSCSlices, 1) … in RequiredDTBCLK()
5872 dml_float_t OutputBpp, in DSCDelayRequirement() argument
5883 if (DSCEnabled == true && OutputBpp != 0) { in DSCDelayRequirement()
5885 …DSCDelayRequirement_val = dscceComputeDelay(DSCInputBitPerComponent, OutputBpp, (dml_uint_t)(dml_c… in DSCDelayRequirement()
5903 dml_print("DML::%s: OutputBpp = %f\n", __func__, OutputBpp); in DSCDelayRequirement()
8250 mode_lib->ms.support.OutputBpp[k] = mode_lib->ms.OutputBppPerState[k]; in dml_core_mode_support()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_vba.h | 507 double OutputBpp[DC__NUM_DPP__MAX]; member
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| A D | display_mode_vba.c | 627 mode_lib->vba.OutputBpp[mode_lib->vba.NumberOfActivePlanes] = in fetch_pipe_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_mode_vba_20.c | 1805 double bpp = mode_lib->vba.OutputBpp[k]; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5115 mode_lib->vba.OutputBpp[k] = in dml20_ModeSupportAndSystemConfigurationFull()
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| A D | display_mode_vba_20v2.c | 1841 double bpp = mode_lib->vba.OutputBpp[k]; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5231 mode_lib->vba.OutputBpp[k] = in dml20v2_ModeSupportAndSystemConfigurationFull()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_mode_vba_21.c | 1797 double bpp = mode_lib->vba.OutputBpp[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5237 mode_lib->vba.OutputBpp[k] = in dml21_ModeSupportAndSystemConfigurationFull()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_mode_vba_31.c | 2254 double BPP = v->OutputBpp[k];
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_mode_vba_314.c | 2272 double BPP = v->OutputBpp[k];
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