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Searched refs:PACKET3_CLEAR_STATE (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dsi_enums.h175 #define PACKET3_CLEAR_STATE 0x12 macro
A Dnvd.h59 #define PACKET3_CLEAR_STATE 0x12 macro
A Dsoc15d.h90 #define PACKET3_CLEAR_STATE 0x12 macro
A Dvid.h116 #define PACKET3_CLEAR_STATE 0x12 macro
A Dcikd.h234 #define PACKET3_CLEAR_STATE 0x12 macro
A Dsid.h1670 #define PACKET3_CLEAR_STATE 0x12 macro
A Dgfx_v6_0.c2034 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v6_0_cp_gfx_start()
2875 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v6_0_get_csb_buffer()
A Dgfx_v7_0.c2505 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v7_0_cp_gfx_start()
3938 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v7_0_get_csb_buffer()
A Dgfx_v11_0.c848 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v11_0_get_csb_buffer()
3470 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v11_0_cp_gfx_start()
3485 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v11_0_cp_gfx_start()
A Dgfx_v8_0.c1250 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_get_csb_buffer()
4186 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_cp_gfx_start()
A Dgfx_v9_0.c1650 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v9_0_get_csb_buffer()
3302 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v9_0_cp_gfx_start()
A Dgfx_v10_0.c4276 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v10_0_get_csb_buffer()
6261 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v10_0_cp_gfx_start()
6281 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v10_0_cp_gfx_start()
/linux/drivers/gpu/drm/radeon/
A Dnid.h1164 #define PACKET3_CLEAR_STATE 0x12 macro
A Dsi.c3582 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
3601 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
4521 case PACKET3_CLEAR_STATE: in si_vm_packet3_gfx_check()
4639 case PACKET3_CLEAR_STATE: in si_vm_packet3_compute_check()
5751 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in si_get_csb_buffer()
A Dsid.h1607 #define PACKET3_CLEAR_STATE 0x12 macro
A Dcikd.h1702 #define PACKET3_CLEAR_STATE 0x12 macro
A Devergreen_cs.c1836 case PACKET3_CLEAR_STATE: in evergreen_packet3_check()
3366 case PACKET3_CLEAR_STATE: in evergreen_vm_packet3_check()
A Devergreend.h1550 #define PACKET3_CLEAR_STATE 0x12 macro
A Dni.c1562 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start()
A Dcik.c4010 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cik_cp_gfx_start()
6760 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in cik_get_csb_buffer()
A Devergreen.c3036 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in evergreen_cp_start()

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