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Searched refs:PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dsi_enums.h253 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dnvd.h206 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dsoc15d.h216 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dvid.h269 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dcikd.h387 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dsid.h1839 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dgfx_v6_0.c2017 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v6_0_cp_gfx_start()
2849 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v6_0_get_csb_buffer()
A Dgfx_v7_0.c2479 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v7_0_cp_gfx_start()
3889 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v7_0_get_csb_buffer()
A Dgfx_v8_0.c1220 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_get_csb_buffer()
4158 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
A Dgfx_v11_0.c818 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v11_0_get_csb_buffer()
3441 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v11_0_cp_gfx_start()
A Dgfx_v9_0.c1626 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v9_0_get_csb_buffer()
3279 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v9_0_cp_gfx_start()
A Dgfx_v10_0.c4246 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v10_0_get_csb_buffer()
6232 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v10_0_cp_gfx_start()
/linux/drivers/gpu/drm/radeon/
A Dnid.h1262 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dsid.h1776 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dcikd.h1854 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Devergreend.h1657 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dni.c1553 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cayman_cp_start()
A Dsi.c3573 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in si_cp_start()
5707 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in si_get_csb_buffer()
A Dcik.c3997 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_cp_gfx_start()
6711 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_get_csb_buffer()
A Devergreen.c3027 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in evergreen_cp_start()

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