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Searched refs:PACKET3_WAIT_REG_MEM (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dsi_enums.h209 #define PACKET3_WAIT_REG_MEM 0x3C macro
A Dnvd.h116 #define PACKET3_WAIT_REG_MEM 0x3C macro
A Dsoc15d.h141 #define PACKET3_WAIT_REG_MEM 0x3C macro
A Dvid.h168 #define PACKET3_WAIT_REG_MEM 0x3C macro
A Dcikd.h287 #define PACKET3_WAIT_REG_MEM 0x3C macro
A Dgfx_v7_0.c2079 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
3103 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_pipeline_sync()
3146 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_vm_flush()
4932 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_wait_reg_mem()
A Dsid.h1719 #define PACKET3_WAIT_REG_MEM 0x3C macro
A Dgfx_v8_0.c6059 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_hdp_flush()
6192 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_pipeline_sync()
6211 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_vm_flush()
6390 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_wait_reg_mem()
A Dgfx_v6_0.c2270 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v6_0_ring_emit_pipeline_sync()
2297 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v6_0_ring_emit_vm_flush()
A Dgfx_v9_4_3.c401 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_4_3_wait_reg_mem()
A Dgfx_v12_0.c386 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v12_0_wait_reg_mem()
A Dgfx_v11_0.c467 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v11_0_wait_reg_mem()
A Dgfx_v9_0.c1150 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_0_wait_reg_mem()
A Dgfx_v10_0.c3928 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v10_0_wait_reg_mem()
/linux/drivers/gpu/drm/radeon/
A Dnid.h1194 #define PACKET3_WAIT_REG_MEM 0x3C macro
A Dsid.h1656 #define PACKET3_WAIT_REG_MEM 0x3C macro
A Dr600_cs.c843 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { in r600_cs_common_vline_parse()
1751 case PACKET3_WAIT_REG_MEM: in r600_packet3_check()
A Dcikd.h1755 #define PACKET3_WAIT_REG_MEM 0x3C macro
A Dsi.c4549 case PACKET3_WAIT_REG_MEM: in si_vm_packet3_gfx_check()
4652 case PACKET3_WAIT_REG_MEM: in si_vm_packet3_compute_check()
5091 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in si_vm_flush()
A Devergreen_cs.c2087 case PACKET3_WAIT_REG_MEM: in evergreen_packet3_check()
3390 case PACKET3_WAIT_REG_MEM: in evergreen_vm_packet3_check()
A Devergreend.h1578 #define PACKET3_WAIT_REG_MEM 0x3C macro
A Dr600d.h1615 #define PACKET3_WAIT_REG_MEM 0x3C macro
A Dni.c2678 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cayman_vm_flush()
A Dcik.c3520 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
5733 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_vm_flush()

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