| /linux/drivers/net/phy/ |
| A D | qt2025.rs | 61 dev.write(C45::new(Mmd::PCS, 0x0026), 0x0e00)?; in probe()
62 dev.write(C45::new(Mmd::PCS, 0x0027), 0x0893)?; in probe()
63 dev.write(C45::new(Mmd::PCS, 0x0028), 0xa528)?; in probe()
64 dev.write(C45::new(Mmd::PCS, 0x0029), 0x0003)?; in probe()
70 dev.write(C45::new(Mmd::PCS, 0xe854), 0x00c0)?; in probe()
81 let mut dst_mmd = Mmd::PCS; in probe()
94 dev.write(C45::new(Mmd::PCS, 0xe854), 0x0040)?; in probe()
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| /linux/drivers/net/pcs/ |
| A D | Kconfig | 3 # PCS Layer Configuration
6 menu "PCS device drivers"
18 This module provides helpers to phylink for managing the Lynx PCS
25 This module provides helpers to phylink for managing the LynxI PCS
33 on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in
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| /linux/Documentation/networking/ |
| A D | sfp-phylink.rst | 219 should be used to configure the MAC when the MAC and PCS are not
252 PCS whose operation is transparent, some other require dedicated PCS
256 Identify if your driver has one or more internal PCS blocks, and/or if
257 your controller can use an external PCS block that might be internally
275 your PCS:
285 Arrange for PCS link state interrupts to be forwarded into
293 otherwise. If a PCS is unable to provide these interrupts, then
294 it should set ``pcs->pcs_poll = true;`` when creating the PCS.
314 Some PCS can be recovered based on firmware information:
333 if ( /* 'interface' needs a PCS to function */ )
[all …]
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| /linux/Documentation/devicetree/bindings/net/ |
| A D | fsl,fman-mdio.yaml | 41 Fman has internal MDIO for internal PCS(Physical
59 set when reading internal PCS registers. MDIO reads to
60 internal PCS registers may result in having the
64 PCS registers through MDIO. As a workaround, all internal
71 - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY.
72 The PCS PHY address should correspond to the value of the appropriate
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| A D | xlnx,axi-ethernet.yaml | 101 - description: MGT reference clock (used by optional internal PCS/PMA PHY)
121 description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
122 modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
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| A D | amd-xgbe.txt | 7 - PCS registers
15 The last interrupt listed should be the PCS auto-negotiation interrupt.
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| A D | fsl,fman-dtsec.yaml | 120 description: The type of each PCS in pcsphy-handle.
124 description: A reference to the (TBI-based) PCS
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| A D | fsl,qoriq-mc-dpmac.yaml | 30 A reference to a node representing a PCS PHY device found on
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| A D | renesas,rzn1-gmac.yaml | 35 phandle pointing to a PCS sub-node compatible with
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| A D | ethernet-controller.yaml | 116 Specifies a reference to a node representing a PCS PHY device on a MDIO
121 The name of each PCS in pcs-handle.
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| /linux/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ |
| A D | mac-phy-support.rst | 54 | MC firmware polling MAC PCS for link |
56 | | PCS | | PCS | | PCS | | PCS | |
65 the MC firmware by polling the MAC PCS. Without the need to register a
187 mode, the MC firmware does not access the PCS registers). One can check for
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| /linux/Documentation/devicetree/bindings/net/pcs/ |
| A D | fsl,lynx-pcs.yaml | 7 title: NXP Lynx PCS
13 NXP Lynx 10G and 28G SerDes have Ethernet PCS devices which can be used as
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| A D | snps,dw-xpcs.yaml | 7 title: Synopsys DesignWare Ethernet PCS
16 controlled by means of the IEEE std. Clause 45 registers set. The PCS can be
21 The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly
83 PCS/PMA layer can be clocked by an internal reference clock source
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| A D | mediatek,sgmiisys.yaml | 13 The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks
47 description: MediaTek LynxI HSGMII PCS
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| /linux/Documentation/devicetree/bindings/phy/ |
| A D | mediatek,mt7988-xfi-tphy.yaml | 14 used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
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| A D | ti-phy.txt | 13 set PCS delay value.
59 register offset to write the PCS delay value.
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| A D | transmit-amplitude.yaml | 7 title: Common PHY and network PCS transmit amplitude property
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| A D | qcom,msm8996-qmp-pcie-phy.yaml | 65 - description: PCS
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| /linux/drivers/phy/mediatek/ |
| A D | Kconfig | 24 1GE and 2.5GE modes via the LynxI PCS, and 5GE and 10GE modes
25 via the USXGMII PCS found in MediaTek SoCs with 10G Ethernet.
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| /linux/Documentation/devicetree/bindings/pci/ |
| A D | snps,dw-pcie-common.yaml | 90 Controller Core-PCS PIPE interface clock. It's normally
91 supplied by an external PCS-PHY.
159 - description: PIPE-interface (Core-PCS) logic reset
164 - description: PCS/PHY block reset
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| A D | snps,dw-pcie-ep.yaml | 85 PHY/PCS configuration registers. Some platforms can have the
86 PCS and PHY CSRs accessible over a dedicated memory mapped
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| /linux/arch/arm/boot/dts/nxp/ls/ |
| A D | ls1021a-tsn.dts | 236 /* SGMII PCS for enet0 */
244 /* SGMII PCS for enet1 */
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| /linux/rust/kernel/net/phy/ |
| A D | reg.rs | 147 pub const PCS: Self = Mmd(uapi::MDIO_MMD_PCS as u8); consts
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| /linux/Documentation/devicetree/bindings/net/dsa/ |
| A D | renesas,rzn1-a5psw.yaml | 73 phandle pointing to a PCS sub-node compatible with
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| /linux/drivers/spi/ |
| A D | spi-atmel.c | 402 SPI_BF(PCS, ~(0x01 << chip_select)) in cs_activate()
408 SPI_BF(PCS, ~(0x01 << chip_select)) in cs_activate()
447 mr = SPI_BFINS(PCS, ~(1 << chip_select), mr); in cs_activate()
468 if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) { in cs_deactivate()
469 mr = SPI_BFINS(PCS, 0xf, mr); in cs_deactivate()
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