Searched refs:PHYASYMCLK_CLOCK_CNTL (Results 1 – 12 of 12) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn30/ |
| A D | dcn30_dccg.h | 39 SR(PHYASYMCLK_CLOCK_CNTL),\
47 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
48 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| A D | dcn31_dccg.h | 38 SR(PHYASYMCLK_CLOCK_CNTL),\
85 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
86 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
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| A D | dcn31_dccg.c | 454 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, in dccg31_set_physymclk()
461 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, in dccg31_set_physymclk()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| A D | dcn35_dccg.h | 60 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN, mask_sh),\
61 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_SRC_SEL, mask_sh),\
139 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN, mask_sh),\
140 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_SRC_SEL, mask_sh),\
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| A D | dcn35_dccg.c | 702 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN, in dccg35_set_physymclk_src_new()
1557 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, in dccg35_set_physymclk()
1561 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, in dccg35_set_physymclk()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| A D | dcn314_dccg.h | 43 SR(PHYASYMCLK_CLOCK_CNTL),\
176 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
177 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| A D | dcn32_dccg.h | 47 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
48 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| A D | dcn401_dccg.h | 47 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN, mask_sh),\
48 DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_SRC_SEL, mask_sh),\
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| A D | dcn401_dccg.c | 279 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, in dccg401_set_physymclk()
286 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, in dccg401_set_physymclk()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| A D | dcn20_dccg.h | 389 uint32_t PHYASYMCLK_CLOCK_CNTL; member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.h | 620 SR(PHYASYMCLK_CLOCK_CNTL), SR(PHYBSYMCLK_CLOCK_CNTL), \
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 1234 SR(PHYASYMCLK_CLOCK_CNTL), SR(PHYBSYMCLK_CLOCK_CNTL), \
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Completed in 33 milliseconds