Searched refs:PHYCSYMCLK_CLOCK_CNTL (Results 1 – 12 of 12) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn30/ |
| A D | dcn30_dccg.h | 41 SR(PHYCSYMCLK_CLOCK_CNTL)
51 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
52 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| A D | dcn31_dccg.h | 40 SR(PHYCSYMCLK_CLOCK_CNTL),\
89 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
90 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
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| A D | dcn31_dccg.c | 488 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, in dccg31_set_physymclk()
495 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, in dccg31_set_physymclk()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| A D | dcn35_dccg.h | 64 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\
65 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\
143 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\
144 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\
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| A D | dcn35_dccg.c | 714 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, in dccg35_set_physymclk_src_new()
1579 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, in dccg35_set_physymclk()
1583 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, in dccg35_set_physymclk()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| A D | dcn314_dccg.h | 45 SR(PHYCSYMCLK_CLOCK_CNTL),\
180 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
181 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| A D | dcn32_dccg.h | 51 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
52 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| A D | dcn401_dccg.h | 51 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\
52 DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\
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| A D | dcn401_dccg.c | 313 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, in dccg401_set_physymclk()
320 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, in dccg401_set_physymclk()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| A D | dcn20_dccg.h | 391 uint32_t PHYCSYMCLK_CLOCK_CNTL; member
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.h | 621 SR(PHYCSYMCLK_CLOCK_CNTL), SR(PHYDSYMCLK_CLOCK_CNTL), \
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.h | 1235 SR(PHYCSYMCLK_CLOCK_CNTL), SR(PHYDSYMCLK_CLOCK_CNTL), \
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Completed in 29 milliseconds