Searched refs:PHYSYMCLK_FORCE_SRC_SYMCLK (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| A D | dcn31_dccg.c | 686 dccg31_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false); in dccg31_init()
687 dccg31_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false); in dccg31_init()
688 dccg31_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false); in dccg31_init()
689 dccg31_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false); in dccg31_init()
690 dccg31_set_physymclk(dccg, 4, PHYSYMCLK_FORCE_SRC_SYMCLK, false); in dccg31_init()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| A D | dcn401_dccg.c | 726 dccg401_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false); in dccg401_init()
727 dccg401_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false); in dccg401_init()
728 dccg401_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false); in dccg401_init()
729 dccg401_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false); in dccg401_init()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | dccg.h | 43 …PHYSYMCLK_FORCE_SRC_SYMCLK, // Select symclk as source of clock which is output to PHY through … enumerator
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| A D | dcn314_dccg.c | 311 PHYSYMCLK_FORCE_SRC_SYMCLK, false); in dccg314_init()
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| /linux/drivers/gpu/drm/amd/include/ |
| A D | soc24_enum.h | 5691 PHYSYMCLK_FORCE_SRC_SYMCLK = 0x00000000, enumerator
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| A D | soc21_enum.h | 5781 PHYSYMCLK_FORCE_SRC_SYMCLK = 0x00000000, enumerator
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Completed in 194 milliseconds