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Searched refs:PIPE_B (Results 1 – 25 of 35) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
A Dintel_vdsc_regs.h31 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
45 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
66 #define _ICL_DSC0_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \
69 #define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \
202 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
205 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
208 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
211 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
227 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
230 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
[all …]
A Dskl_watermark.c869 [PIPE_B] = BIT(DBUF_S1),
876 [PIPE_B] = BIT(DBUF_S2),
895 [PIPE_B] = BIT(DBUF_S1),
903 [PIPE_B] = BIT(DBUF_S1),
939 [PIPE_B] = BIT(DBUF_S1),
958 [PIPE_B] = BIT(DBUF_S1),
966 [PIPE_B] = BIT(DBUF_S1),
986 [PIPE_B] = BIT(DBUF_S1),
994 [PIPE_B] = BIT(DBUF_S1),
1016 [PIPE_B] = BIT(DBUF_S1),
[all …]
A Dintel_display_device.c153 [PIPE_B] = CURSOR_B_OFFSET, \
159 [PIPE_B] = CURSOR_B_OFFSET, \
166 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
173 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
218 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
441 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
897 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
1057 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
1557 display_runtime->num_scalers[PIPE_B] = 2; in __intel_display_device_info_runtime_init()
1581 display_runtime->num_sprites[PIPE_B] = 2; in __intel_display_device_info_runtime_init()
[all …]
A Dintel_display_limits.h18 PIPE_B, enumerator
35 TRANSCODER_B = PIPE_B,
A Dintel_dpio_phy.c695 case PIPE_B: in vlv_pipe_to_phy()
711 case PIPE_B: in vlv_pipe_to_channel()
874 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_phy_pre_pll_enable()
886 if (pipe != PIPE_B) { in chv_phy_pre_pll_enable()
907 if (pipe == PIPE_B) in chv_phy_pre_pll_enable()
916 if (pipe == PIPE_B) in chv_phy_pre_pll_enable()
929 if (pipe == PIPE_B) in chv_phy_pre_pll_enable()
1038 if (pipe != PIPE_B) { in chv_phy_post_pll_disable()
1134 if (pipe == PIPE_B) in vlv_phy_pre_encoder_enable()
A Di9xx_wm.c277 case PIPE_B: in vlv_get_fifo_size()
725 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in g4x_write_wm_values()
726 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in g4x_write_wm_values()
732 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | in g4x_write_wm_values()
775 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in vlv_write_wm_values()
776 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in vlv_write_wm_values()
1808 case PIPE_B: in vlv_atomic_update_fifo()
3227 if (dirty & WM_DIRTY_PIPE(PIPE_B)) in ilk_write_wm_values()
3529 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); in g4x_read_wm_values()
3530 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB); in g4x_read_wm_values()
[all …]
A Dintel_display_power_map.c150 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
394 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
473 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
576 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
752 .irq_pipe_mask = BIT(PIPE_B),
918 .irq_pipe_mask = BIT(PIPE_B),
1073 .irq_pipe_mask = BIT(PIPE_B),
1168 .irq_pipe_mask = BIT(PIPE_B),
1344 .irq_pipe_mask = BIT(PIPE_B),
1501 .irq_pipe_mask = BIT(PIPE_B),
A Dintel_fdi.c160 crtc = intel_crtc_for_pipe(i915, PIPE_B); in intel_fdi_add_affected_crtcs()
171 BIT(PIPE_B)); in intel_fdi_add_affected_crtcs()
222 case PIPE_B: in ilk_check_fdi_lanes()
247 other_crtc = intel_crtc_for_pipe(dev_priv, PIPE_B); in ilk_check_fdi_lanes()
257 *pipe_to_reduce = PIPE_B; in ilk_check_fdi_lanes()
425 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & in cpt_set_fdi_bc_bifurcation()
449 case PIPE_B: in ivb_update_fdi_bc_bifurcation()
A Dintel_display_trace.h48 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
77 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
207 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
A Dintel_pipe_crc.c178 case PIPE_B: in vlv_pipe_crc_ctl_reg()
239 case PIPE_B: in vlv_undo_pipe_scramble_reset()
A Dintel_display_power_well.c1053 if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1054 i830_enable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_enable()
1060 i830_disable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_disable()
1068 intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; in i830_pipes_power_well_enabled()
1365 (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1493 assert_pll_disabled(dev_priv, PIPE_B); in chv_dpio_cmn_power_well_disable()
A Dintel_pch_display.c52 HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_dp_disabled()
71 HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_hdmi_disabled()
A Dg4x_hdmi.c405 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { in intel_disable_hdmi()
771 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
A Dintel_display_irq.c293 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
449 case PIPE_B: in i9xx_pipestat_irq_ack()
625 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); in ibx_irq_handler()
1004 pipe = PIPE_B; in gen11_dsi_te_interrupt_handler()
A Dintel_pps.c43 case PIPE_B: in pps_name()
172 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
300 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
1159 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
A Dicl_dsi.c815 case PIPE_B: in gen11_dsi_configure_transcoder()
1224 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) in icl_apply_kvmr_pipe_a_wa()
1571 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && in gen11_dsi_sync_state()
1713 *pipe = PIPE_B; in gen11_dsi_get_hw_state()
A Dintel_sprite.c420 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) in vlv_sprite_update_arm()
1613 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
1666 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
A Di9xx_plane.c993 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_primary_plane_create()
1097 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && in i9xx_get_initial_plane_config()
A Dvlv_dsi.c976 TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; in intel_dsi_get_hw_state()
1001 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1945 encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
A Dg4x_dp.c454 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { in intel_dp_link_down()
1402 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
/linux/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c208 MMIO_D(SPRCTL(PIPE_B)); in iterate_generic_mmio()
209 MMIO_D(SPRLINOFF(PIPE_B)); in iterate_generic_mmio()
210 MMIO_D(SPRSTRIDE(PIPE_B)); in iterate_generic_mmio()
211 MMIO_D(SPRPOS(PIPE_B)); in iterate_generic_mmio()
212 MMIO_D(SPRSIZE(PIPE_B)); in iterate_generic_mmio()
213 MMIO_D(SPRKEYVAL(PIPE_B)); in iterate_generic_mmio()
214 MMIO_D(SPRKEYMSK(PIPE_B)); in iterate_generic_mmio()
215 MMIO_D(SPRSURF(PIPE_B)); in iterate_generic_mmio()
216 MMIO_D(SPRKEYMAX(PIPE_B)); in iterate_generic_mmio()
218 MMIO_D(SPRSCALE(PIPE_B)); in iterate_generic_mmio()
[all …]
A Di915_irq.c904 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
1086 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
1212 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/linux/drivers/gpu/drm/i915/gvt/
A Dhandlers.c2286 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2295 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
2477 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2479 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2481 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2640 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2641 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2642 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2643 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2651 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
[all …]
A Dreg.h70 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
79 (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
A Ddisplay.c57 pipe = PIPE_B; in get_edp_pipe()
635 [PIPE_B] = PIPE_B_VBLANK, in emulate_vblank_on_pipe()

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