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Searched refs:PLL (Results 1 – 25 of 283) sorted by relevance

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/linux/drivers/clk/mediatek/
A Dclk-mt8195-apmixedsys.c62 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
64 PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
66 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
68 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
80 PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0100, 0x0110, 0,
94 PLL(CLK_APMIXED_APLL1, "apll1", 0x07c0, 0x0dc0, 0,
96 PLL(CLK_APMIXED_APLL2, "apll2", 0x0780, 0x0dc4, 0,
98 PLL(CLK_APMIXED_APLL3, "apll3", 0x0760, 0x0dc8, 0,
100 PLL(CLK_APMIXED_APLL4, "apll4", 0x0740, 0x0dcc, 0,
104 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x0350, 0,
[all …]
A Dclk-mt8188-apmixedsys.c61 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x044C, 0x0458, 0,
63 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
65 PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x0524, 0x0530, 0,
67 PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x0534, 0x0540, 0,
73 PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0554, 0x0560, 0,
79 PLL(CLK_APMIXED_APLL1, "apll1", 0x0304, 0x0314, 0,
81 PLL(CLK_APMIXED_APLL2, "apll2", 0x0318, 0x0328, 0,
83 PLL(CLK_APMIXED_APLL3, "apll3", 0x032C, 0x033C, 0,
85 PLL(CLK_APMIXED_APLL4, "apll4", 0x0404, 0x0414, 0,
87 PLL(CLK_APMIXED_APLL5, "apll5", 0x0418, 0x0428, 0,
[all …]
A Dclk-mt7988-apmixed.c22 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg, \ macro
48 PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,
50 PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,
52 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
54 PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
56 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,
60 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0,
62 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0,
66 PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32,
68 PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32,
[all …]
A Dclk-mt8186-apmixedsys.c19 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ macro
55 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0224, 0x0230, 0,
61 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x038C, 0x0398, 0,
63 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0254, 0x0260, 0,
65 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x035C, 0x0368, 0,
67 PLL(CLK_APMIXED_NNA2PLL, "nna2pll", 0x036C, 0x0378, 0,
69 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x0304, 0x0310, 0,
71 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0314, 0x0320, 0,
73 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0264, 0x0270, 0,
75 PLL(CLK_APMIXED_APLL1, "apll1", 0x0334, 0x0344, 0,
[all …]
A Dclk-mt8135-apmixedsys.c20 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg,… macro
38 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0),
39 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
40 …PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x2…
41 …PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x23…
42 …PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, …
43 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
44 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0),
45 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
46 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
[all …]
A Dclk-mt2712-apmixedsys.c44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
80 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
82 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
86 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
88 PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,
90 PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,
92 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100,
94 PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100,
96 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
98 PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100,
[all …]
A Dclk-mt8173-apmixedsys.c44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
61 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO,
63 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO,
65 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21,
67 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7,
71 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
72 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
73 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
74 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
76 PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
[all …]
A Dclk-mt7986-apmixed.c36 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
43 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
45 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
47 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x0, 0, 32,
49 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x0, 0, 32,
51 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x0, 0,
53 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x0, 0, 32,
55 PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x0, 0, 32, 0x0260,
57 PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x0, 0, 32,
A Dclk-mt7981-apmixed.c38 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
45 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
47 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
49 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
51 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
53 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
55 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
57 PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
59 PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
A Dclk-mt7622-apmixedsys.c41 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
59 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
61 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
63 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
65 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
67 PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
69 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0,
71 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0,
73 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0,
75 PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
A Dclk-mt6795-apmixedsys.c26 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
47 PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO,
49 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
51 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR,
53 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0),
54 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
55 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
56 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
57 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
59 PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a8, 0x2a4, 0),
[all …]
A Dclk-mt8365-apmixedsys.c45 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
85 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001,
87 PLL(CLK_APMIXED_UNIVPLL, "univpll2", 0x0208, 0x0214, 0xFF000001,
91 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22,
93 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22,
95 PLL(CLK_APMIXED_APLL1, "apll1", 0x031C, 0x032C, 0x00000001, 0, 32,
97 PLL(CLK_APMIXED_APLL2, "apll2", 0x0360, 0x0370, 0x00000001, 0, 32,
99 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0374, 0x0380, 0x00000001, 0, 22,
103 PLL(CLK_APMIXED_APUPLL, "apupll", 0x03A0, 0x03AC, 0x00000001, 0, 22,
A Dclk-mt8167-apmixedsys.c42 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
59 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0,
61 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
63 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000,
67 PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0,
69 PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0,
71 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0, 0,
73 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0, 0,
A Dclk-mt8183-apmixedsys.c81 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ macro
117 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0,
120 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0,
123 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0,
129 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0,
131 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0,
133 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0,
136 PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0,
138 PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0,
A Dclk-mt8516-apmixedsys.c43 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
60 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0,
62 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
64 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000,
68 PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0,
70 PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0,
A Dclk-mt8195-apusys_pll.c28 #define PLL(_id, _name, _reg, _pwr_reg, _pd_reg, _pcw_reg) { \ macro
53 PLL(CLK_APUSYS_PLL_APUPLL, "apusys_pll_apupll", 0x008, 0x014, 0x00c, 0x00c),
54 PLL(CLK_APUSYS_PLL_NPUPLL, "apusys_pll_npupll", 0x018, 0x024, 0x01c, 0x01c),
55 PLL(CLK_APUSYS_PLL_APUPLL1, "apusys_pll_apupll1", 0x028, 0x034, 0x02c, 0x02c),
56 PLL(CLK_APUSYS_PLL_APUPLL2, "apusys_pll_apupll2", 0x038, 0x044, 0x03c, 0x03c),
/linux/Documentation/devicetree/bindings/clock/
A Dqcom,mmcc.yaml83 - description: PLL 3 clock
84 - description: PLL 3 Vote clock
89 - description: HDMI phy PLL clock
149 - description: HDMI phy PLL clock
188 - description: HDMI phy PLL clock
232 - description: Global PLL 0 clock
239 - description: HDMI phy PLL clock
263 - description: Global PLL 0 clock
269 - description: HDMI phy PLL clock
292 - description: Global PLL 0 clock
[all …]
A Dsilabs,si5351.yaml56 A list of cell pairs containing a PLL index and its source. Allows to
60 - description: PLL A (0) or PLL B (1)
62 - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).
72 - description: PLL A (0) or PLL B (1)
75 Reset mode for the PLL. Mode can be one of:
77 0 - reset whenever PLL rate is adjusted (default mode)
78 1 - do not reset when PLL rate is adjusted
80 In mode 1, the PLL is only reset if the silabs,pll-reset is
82 the PLL. This mode may be preferable if output clocks are expected
123 The frequency of the source PLL is allowed to be changed by the
[all …]
A Dqcom,a53pll.yaml7 title: Qualcomm A53 PLL clock
13 The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for
55 # Example 1 - A53 PLL found on MSM8916 devices
62 # Example 2 - A53 PLL found on IPQ6018 devices
A Dxgene.txt9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
16 Required properties for SoC or PCP PLL clocks:
17 - reg : shall be the physical PLL register address for the pll clock.
21 - clock-output-names : shall be the name of the PLL referenced by derive
23 Optional properties for PLL clocks:
24 - clock-names : shall be the name of the PLL. If missing, use the device name.
32 Optional properties for PLL clocks:
A Dti,cdce925.yaml15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
54 "^PLL[1-4]$":
97 /* PLL options to get SSC 1% centered */
A Dbaikal,bt1-ccu-pll.yaml8 title: Baikal-T1 Clock Control Unit PLL
52 with an interface wrapper (so called safe PLL' clocks switcher) to simplify
53 the PLL configuration procedure. The PLLs work as depicted on the next
71 divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
72 output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
73 the binding supports the PLL dividers configuration in accordance with a
81 The CCU PLL dts-node uses the common clock bindings with no custom
83 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
113 # Clock Control Unit PLL node:
A Dsophgo,sg2042-clkgen.yaml21 - description: Main PLL
22 - description: Fixed PLL
23 - description: DDR PLL 0
24 - description: DDR PLL 1
A Ddove-divider-clock.txt1 PLL divider based Dove clocks
3 Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
18 - reg : shall be the register address of the Core PLL and Clock Divider
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
/linux/drivers/clk/sophgo/
A DKconfig14 tristate "Sophgo SG2042 PLL clock support"
17 This driver supports the PLL clock controller on the
20 PLL, DDR PLL 0 and DDR PLL 1 respectively.
27 Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock
28 because it uses PLL clocks as input.

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