Searched refs:PLL1 (Results 1 – 19 of 19) sorted by relevance
| /linux/sound/soc/codecs/ |
| A D | ak4642.c | 115 #define PLL1 (1 << 5) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
351 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
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| /linux/Documentation/devicetree/bindings/clock/ |
| A D | microchip,mpfs-ccc.yaml | 25 - description: PLL1's control registers
37 - description: PLL1's refclk0
38 - description: PLL1's refclk1
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| A D | silabs,si5351.yaml | 216 /* Use XTAL input as source of PLL0 and PLL1 */
219 /* Don't reset PLL1 on rate adjustment */
242 * - PLL1 as clock source of multisynth 1
244 * - Multisynth 1 can change PLL1
245 * - Reset PLL1 when enabling this clock output
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| A D | starfive,jh7110-syscrg.yaml | 31 - description: PLL1
45 - description: PLL1
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| A D | st,nomadik.txt | 30 - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
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| /linux/Documentation/arch/arm/sunxi/ |
| A D | clocks.rst | 20 PLL1
31 PLL1 |
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| /linux/include/dt-bindings/clock/ |
| A D | qcom,mmcc-msm8960.h | 126 #define PLL1 117 macro
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| A D | stm32mp13-clks.h | 19 #define PLL1 6 macro
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| A D | stm32mp1-clks.h | 183 #define PLL1 176 macro
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| /linux/Documentation/devicetree/bindings/phy/ |
| A D | phy-cadence-torrent.yaml | 39 PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
42 Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used.
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| /linux/Documentation/devicetree/bindings/clock/ti/davinci/ |
| A D | pll.txt | 10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
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| /linux/Documentation/devicetree/bindings/clock/st/ |
| A D | st,flexgen.txt | 31 | | |PLL1 | | | | | | | | | |
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| /linux/drivers/media/dvb-frontends/ |
| A D | zl10039.c | 40 PLL1, enumerator
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| /linux/arch/arm/boot/dts/st/ |
| A D | ste-nomadik-stn8815.dtsi | 196 * that is parent of TIMCLK, PLL1 and PLL2
218 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
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| /linux/drivers/clk/nxp/ |
| A D | clk-lpc18xx-cgu.c | 518 LPC1XX_CGU_CLK_PLL(PLL1, pll1_src_ids, pll1_ops),
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| /linux/arch/mips/boot/dts/ingenic/ |
| A D | gcw0.dts | 442 * Put high-speed peripherals under PLL1, such that we can change the
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| /linux/drivers/clk/stm32/ |
| A D | clk-stm32mp1.c | 1777 PLL(PLL1, "pll1", ref12_parents, 0, RCC_PLL1CR, RCC_RCK12SELR),
2097 PLL1,
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| /linux/drivers/clk/ |
| A D | Kconfig | 200 Y2 and Y3 derive from PLL1
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| /linux/arch/arm64/boot/dts/freescale/ |
| A D | imx8mp-dhcom-som.dtsi | 518 * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,
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