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Searched refs:PLL3 (Results 1 – 17 of 17) sorted by relevance

/linux/sound/soc/codecs/
A Dak4642.c113 #define PLL3 (1 << 7) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
357 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
363 pll = PLL3; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
/linux/arch/arm/boot/dts/st/
A Dstm32mp151c-mecio1r0.dts46 assigned-clock-rates = <125000000>; /* Clock PLL3 to 625Mhz in tf-a. */
/linux/include/dt-bindings/clock/
A Dstm32mp13-clks.h21 #define PLL3 8 macro
A Dstm32mp1-clks.h185 #define PLL3 178 macro
A Dqcom,gcc-ipq806x.h231 #define PLL3 222 macro
A Dqcom,gcc-mdm9615.h288 #define PLL3 278 macro
A Dqcom,gcc-msm8960.h286 #define PLL3 278 macro
/linux/drivers/media/dvb-frontends/
A Dzl10039.c42 PLL3, enumerator
/linux/Documentation/devicetree/bindings/clock/
A Dst,stm32mp25-rcc.yaml114 - description: CK_SCMI_PLL3 PLL3 clock
/linux/arch/arm/boot/dts/qcom/
A Dqcom-msm8960.dtsi168 <&gcc PLL3>,
A Dqcom-apq8064.dtsi734 <&gcc PLL3>,
/linux/drivers/net/wireless/ath/ath9k/
A Dhw.c740 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
742 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
756 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; in ar9003_get_pll_sqsum_dvc()
A Dreg.h1375 #define PLL3 0x16188 macro
/linux/drivers/clk/stm32/
A Dclk-stm32mp25.c123 PLL3, enumerator
747 .hw.init = CLK_HW_INIT_INDEX("ck_ker_gpu", PLL3, &clk_stm32_gate_ops, 0),
A Dclk-stm32mp1.c1779 PLL(PLL3, "pll3", ref3_parents, 0, RCC_PLL3CR, RCC_RCK3SELR),
/linux/drivers/clk/qcom/
A Dgcc-msm8960.c3243 [PLL3] = &pll3.clkr,
3471 [PLL3] = &pll3.clkr,
A Dgcc-ipq806x.c3069 [PLL3] = &pll3.clkr,

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