Searched refs:PLL_DIV (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/clk/x86/ |
| A D | clk-lgm.c | 114 #define PLL_DIV(x) ((x) + 0x04) macro
204 PLL_DIV(CGU_PLL2_CFG0), 0, PLL_DIV_WIDTH, 24, 1, 0, 0,
210 PLL_DIV(CGU_PLL0CZ_CFG0), 4, PLL_DIV_WIDTH, 25,
217 CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM0_CFG0),
220 CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM1_CFG0),
230 (CLK_IGNORE_UNUSED|CLK_IS_CRITICAL), PLL_DIV(CGU_PLL0B_CFG0),
408 PLL_DIV(CGU_LJPLL3_CFG0), 0, PLL_DDIV_WIDTH,
411 PLL_DIV(CGU_LJPLL3_CFG0), 6, PLL_DDIV_WIDTH,
414 PLL_DIV(CGU_LJPLL3_CFG0), 12, PLL_DDIV_WIDTH,
417 PLL_DIV(CGU_LJPLL3_CFG0), 18, PLL_DDIV_WIDTH,
[all …]
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| /linux/drivers/clk/at91/ |
| A D | clk-pll.c | 19 #define PLL_DIV(reg) ((reg) & PLL_DIV_MASK) macro
72 div = PLL_DIV(pllr); in clk_pll_prepare()
288 calc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) * in clk_pll_restore_context()
343 pll->div = PLL_DIV(pllr); in at91_clk_register_pll()
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| /linux/drivers/mfd/ |
| A D | db8500-prcmu.c | 462 PLL_DIV enumerator
470 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
477 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
478 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
479 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
480 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
481 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
482 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
484 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
490 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
[all …]
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| /linux/drivers/clk/ |
| A D | clk-sparx5.c | 19 #define PLL_DIV GENMASK(7, 0) macro
179 val |= FIELD_PREP(PLL_DIV, conf.div); in s5_pll_set_rate()
202 conf.div = FIELD_GET(PLL_DIV, val); in s5_pll_recalc_rate()
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| /linux/drivers/clk/imx/ |
| A D | clk-fracn-gppll.c | 32 #define PLL_DIV 0x60 macro
169 pll_div = readl_relaxed(pll->base + PLL_DIV); in clk_fracn_gppll_recalc_rate()
256 writel_relaxed(pll_div, pll->base + PLL_DIV); in clk_fracn_gppll_set_rate()
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| /linux/drivers/gpu/drm/bridge/ |
| A D | chipone-icn6211.c | 82 #define PLL_DIV(n) (0x63 + ((n) & 0x3)) /* 0..2 */ macro
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