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Searched refs:PORT_B (Results 1 – 25 of 31) sorted by relevance

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/linux/drivers/gpu/drm/i915/gvt/
A Ddisplay.c307 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= in emulate_monitor_status_change()
309 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= in emulate_monitor_status_change()
316 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= in emulate_monitor_status_change()
318 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= in emulate_monitor_status_change()
323 (PORT_B << TRANS_DDI_PORT_SHIFT) | in emulate_monitor_status_change()
354 (PORT_B << TRANS_DDI_PORT_SHIFT) | in emulate_monitor_status_change()
410 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); in emulate_monitor_status_change()
414 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); in emulate_monitor_status_change()
421 (PORT_B << TRANS_DDI_PORT_SHIFT) | in emulate_monitor_status_change()
424 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= in emulate_monitor_status_change()
[all …]
A Dedid.c89 port = PORT_B; in cnp_get_port_from_gmbus0()
105 port = PORT_B; in bxt_get_port_from_gmbus0()
123 port = PORT_B; in get_port_from_gmbus0()
A Dmmio.c279 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= in intel_vgpu_reset_mmio()
281 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= in intel_vgpu_reset_mmio()
A Dvgpu.c376 ret = intel_gvt_set_edid(vgpu, PORT_B); in intel_gvt_create_vgpu()
A Dhandlers.c556 case PORT_B: in bxt_vgpu_get_dp_bitrate()
662 if (port != PORT_B && port != PORT_D) { in vgpu_update_refresh_rate()
949 calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
2351 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2357 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2363 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); in init_generic_mmio_info()
2767 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, in init_bxt_mmio_info()
/linux/drivers/gpu/drm/i915/display/
A Dintel_display_device.c248 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
257 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
267 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
282 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
368 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
738 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
935 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
951 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
974 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1068 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
[all …]
A Dintel_pch_display.c81 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B); in assert_pch_ports_disabled()
96 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB); in assert_pch_ports_disabled()
165 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B); in ibx_sanitize_pch_ports()
170 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB); in ibx_sanitize_pch_ports()
435 drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D); in ilk_pch_enable()
A Dintel_display_limits.h86 PORT_B, enumerator
A Dintel_lpe_audio.c339 ppdata = &pdata->port[port - PORT_B]; in intel_lpe_audio_notify()
366 pdata->notify_audio_lpe(dev_priv->display.audio.lpe.platdev, port - PORT_B); in intel_lpe_audio_notify()
A Dintel_dpio_phy.c173 [DPIO_CH0] = { .port = PORT_B },
196 [DPIO_CH0] = { .port = PORT_B },
666 case PORT_B: in vlv_dig_port_to_channel()
680 case PORT_B: in vlv_dig_port_to_phy()
A Dicl_dsi.c225 port = PORT_B; in icl_dsi_frame_update()
1090 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) in gen11_dsi_config_util_pin()
1512 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_is_periodic_cmd_mode()
1524 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) in gen11_dsi_get_cmd_mode_config()
1527 else if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_get_cmd_mode_config()
1651 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_compute_config()
2028 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); in icl_dsi_init()
A Dintel_audio_regs.h161 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \
A Dintel_sdvo.c234 if (intel_sdvo->base.port == PORT_B) in intel_sdvo_write_sdvox()
412 #define SDVO_NAME(svdo) ((svdo)->base.port == PORT_B ? "SDVOB" : "SDVOC")
1627 if (intel_sdvo->base.port == PORT_B) in intel_sdvo_pre_enable()
2621 if (sdvo->base.port == PORT_B) in intel_sdvo_select_ddc_bus()
2644 if (sdvo->base.port == PORT_B) in intel_sdvo_select_i2c_bus()
2688 if (sdvo->base.port == PORT_B) { in intel_sdvo_get_target_addr()
2715 if (sdvo->base.port == PORT_B) in intel_sdvo_get_target_addr()
3369 return port == PORT_B; in is_sdvo_port_valid()
3371 return port == PORT_B || port == PORT_C; in is_sdvo_port_valid()
3468 if (intel_sdvo->base.port == PORT_B) in intel_sdvo_init()
A Dg4x_hdmi.c675 return port == PORT_B || port == PORT_C; in is_hdmi_port_valid()
677 return port == PORT_B || port == PORT_C || port == PORT_D; in is_hdmi_port_valid()
A Dintel_dsi_vbt.c93 if (intel_dsi->ports & BIT(PORT_B)) in intel_dsi_seq_port_to_port()
94 return PORT_B; in intel_dsi_seq_port_to_port()
A Dintel_hdmi.c2698 case PORT_B: in chv_encoder_to_ddc_pin()
2721 case PORT_B: in bxt_encoder_to_ddc_pin()
2741 case PORT_B: in cnp_encoder_to_ddc_pin()
2846 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); in adls_encoder_to_ddc_pin()
2864 case PORT_B: in g4x_encoder_to_ddc_pin()
A Dintel_bios.c1644 enum port port_bc = DISPLAY_VER(display) >= 11 ? PORT_B : PORT_C; in parse_dsi_backlight_ports()
2343 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, in dvo_port_to_port()
2358 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, in dvo_port_to_port()
2369 [PORT_B] = { -1 }, in dvo_port_to_port()
2378 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, in dvo_port_to_port()
2418 return PORT_B; in dsi_dvo_port_to_port()
A Dintel_pipe_crc.c104 case PORT_B: in i9xx_pipe_crc_auto_source()
A Dintel_display_irq.c984 PORT_A : PORT_B; in gen11_dsi_te_interrupt_handler()
1017 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; in gen11_dsi_te_interrupt_handler()
1347 port = PORT_B; in gen11_dsi_configure_te()
A Dintel_dvo.c105 .port = PORT_B,
A Dintel_display.c386 case PORT_B: in vlv_wait_port_ready()
7827 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); in intel_setup_outputs()
7829 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); in intel_setup_outputs()
7831 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); in intel_setup_outputs()
7866 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); in intel_setup_outputs()
7867 has_port = intel_bios_is_port_present(display, PORT_B); in intel_setup_outputs()
7869 has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); in intel_setup_outputs()
7871 g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); in intel_setup_outputs()
7906 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); in intel_setup_outputs()
7910 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); in intel_setup_outputs()
[all …]
A Dintel_display.h132 case PORT_B: in port_identifier()
A Dintel_display_debugfs.c1121 lpsp_capable = encoder->port <= PORT_B; in i915_lpsp_capability_show()
1128 lpsp_capable = encoder->port <= PORT_B; in i915_lpsp_capability_show()
/linux/drivers/staging/media/tegra-video/
A Dcsi.h30 PORT_B, enumerator
/linux/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c491 MMIO_D(PORT_CLK_SEL(PORT_B)); in iterate_generic_mmio()
522 MMIO_D(DDI_BUF_CTL(PORT_B)); in iterate_generic_mmio()
527 MMIO_D(DP_TP_CTL(PORT_B)); in iterate_generic_mmio()
532 MMIO_D(DP_TP_STATUS(PORT_B)); in iterate_generic_mmio()
1134 MMIO_D(BXT_PHY_CTL(PORT_B)); in iterate_bxt_mmio()
1137 MMIO_D(BXT_PORT_PLL_ENABLE(PORT_B)); in iterate_bxt_mmio()

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